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path: root/llvm/lib/CodeGen/MachineInstr.cpp
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2022-06-25CodeGen: Use else if between Value and PseudoSourceValue casesMatt Arsenault1-3/+2
2022-03-16[NFC][CodeGen] Rename some functions in MachineInstr.h and remove duplicated ...Shengchen Kan1-14/+5
2022-03-16Cleanup codegen includesserge-sans-paille1-17/+0
2022-03-10Revert "Cleanup codegen includes"Nico Weber1-0/+17
2022-03-10Cleanup codegen includesserge-sans-paille1-17/+0
2022-03-01[nfc][codegen] Move RegisterBank[Info].h under CodeGenMircea Trofin1-1/+1
2022-02-21MIR: Start diagnosing too many operands on an instructionMatt Arsenault1-6/+2
2021-12-06[NFC][MachineInstr] Rename some vars to conform to coding styleMircea Trofin1-6/+6
2021-12-05[GlobalISel] Allow DBG_VALUE to use undefined vregs before LiveDebugValues.Jack Andersen1-20/+0
2021-11-25[llvm] Use range-based for loops (NFC)Kazu Hirata1-4/+2
2021-10-07[MachineInstr] Move MIParser's DBG_VALUE RegState::Debug invariant into Machi...Jack Andersen1-4/+7
2021-07-22[clang] Use i64 for the !srcloc metadata on asm IR nodes.Simon Tatham1-1/+1
2021-07-01[DebugInfo][InstrRef][1/4] Support transformations that widen valuesJeremy Morse1-0/+6
2021-04-09[NFC][AA] Prepare to convert AliasResult to class with PartialAlias offset.dfukalov1-3/+1
2021-03-10[DebugInfo] Handle DBG_VALUES with multiple variable location operands in MIRStephen Tozer1-11/+39
2021-03-05Reapply "[DebugInfo] Add new instruction and DIExpression operator for varia...Stephen Tozer1-28/+91
2021-03-04Revert "[DebugInfo] Add new instruction and DIExpression operator for variadi...Stephen Tozer1-94/+32
2021-03-04[DebugInfo] Add new instruction and DIExpression operator for variadic debug ...gbtozers1-32/+94
2021-02-15[CodeGen] Use range-based for loops (NFC)Kazu Hirata1-3/+2
2021-02-10[CSSPGO] Unblock optimizations with pseudo probe instrumentation.Hongtao Yu1-1/+2
2021-01-25[XRay] Support DW_TAG_call_site and delete unneeded PATCHABLE_EVENT_CALL/PATC...Fangrui Song1-2/+0
2021-01-06[NFC] Don't copy MachineFrameInfo on each invocation of HasAliasSanjoy Das1-74/+71
2020-12-09Prevent FENTRY_CALL reorderingIlya Leoshkevich1-0/+1
2020-11-03[MachineInstr] Add support for instructions with multiple memory operands.Michael Liao1-65/+80
2020-10-15[Statepoints] Unlimited tied operands.Denis Antrushin1-4/+28
2020-10-07[MachineInstr] exclude call instruction in mayAliasChen Zheng1-0/+5
2020-09-14[DebugInstrRef][1/9] Add fields for instr-ref variable locationsJeremy Morse1-9/+23
2020-08-20Fix a couple of typos. NFCJon Roelofs1-1/+1
2020-07-17[ScheduleDAG] Move DBG_VALUEs after first term forward.Florian Hahn1-0/+4
2020-06-22[DebugInfo] Update MachineInstr to help support variadic DBG_VALUE instructionsstozer1-12/+26
2020-05-29Add NoMerge MIFlag to avoid MIR branch foldingZequan Wu1-0/+2
2020-05-22Revert "[CodeGen] Add support for multiple memory operands in MachineInstr::m...Jean-Michel Gorius1-72/+65
2020-05-21[CodeGen] Add support for multiple memory operands in MachineInstr::mayAliasJean-Michel Gorius1-65/+72
2020-04-24[llvm][CodeGen] Check for memory instructions when querying for alias statusJean-Michel Gorius1-0/+4
2020-04-16[MIR] Add comments to INLINEASM immediate flag MachineOperandsKonstantin Schwarz1-32/+3
2020-02-29[MachineInst] Remove dead code. NFCI.Simon Pilgrim1-9/+0
2020-02-29Make argument const to silence cppcheck warning. NFCI.Simon Pilgrim1-1/+1
2020-02-27[CallSiteInfo] Handle bundles when updating call site infoDjordje Todorovic1-2/+8
2020-02-25[MachineInstr] Add a dumpr methodQuentin Colombet1-0/+32
2020-02-07[MachineInstr] Add isCandidateForCallSiteEntry predicateVedant Kumar1-0/+14
2020-01-11moveOperands - assert Src/Dst MachineOperands are non-null.Simon Pilgrim1-1/+1
2020-01-10[FPEnv] Invert sense of MIFlag::FPExcept flagUlrich Weigand1-2/+2
2020-01-10[MIR] Fix cyclic dependency of MIR formatterPeng Guo1-6/+3
2020-01-08Revert "Revert "[MIR] Target specific MIR formating and parsing""Daniel Sanders1-8/+11
2020-01-08Revert "[MIR] Target specific MIR formating and parsing"Nico Weber1-11/+8
2020-01-08[MIR] Target specific MIR formating and parsingPeng Guo1-8/+11
2020-01-08Revert "[MIR] Target specific MIR formating and parsing"Daniel Sanders1-11/+8
2020-01-08[MIR] Target specific MIR formating and parsingPeng Guo1-8/+11
2019-11-15[CodeGen] Increase the size of a SmallVectorJay Foad1-1/+1
2019-11-05[MIR] Add MIR parsing for heap alloc site instruction markersAmy Huang1-2/+3
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