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path: root/llvm/lib/CodeGen/MachineCSE.cpp
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2021-05-05[MachineCSE][NFC]: Refactor and comment on preventing CSE for isConvergent in...Michael Kitzan1-5/+27
2021-04-23[MachineCSE] Prevent CSE of non-local convergent instrsMichael Kitzan1-1/+5
2021-01-21[CodeGen] Use llvm::append_range (NFC)Kazu Hirata1-4/+2
2020-10-28[NFC] Use [MC]Register in CSE & LICMGaurav Jain1-17/+17
2020-09-26MachineCSE.cpp - use auto const& iterators in for-range loops to avoid copies...Simon Pilgrim1-2/+2
2020-09-21MachineCSE.cpp - use auto const& iterator in for-range loop to avoid copies. ...Simon Pilgrim1-2/+2
2020-07-06DomTree: Remove getChildren() accessorNicolai Hähnle1-5/+3
2020-04-06[MachineCSE] Don't carry the wrong location when hoistingDavide Italiano1-0/+7
2019-11-13Sink all InitializePasses.h includesReid Kleckner1-0/+1
2019-09-02[DebugInfo] LiveDebugValues: correctly discriminate kinds of variable locationsJeremy Morse1-3/+5
2019-08-15Apply llvm-prefer-register-over-unsigned from clang-tidy to LLVMDaniel Sanders1-9/+9
2019-08-07[MachineCSE][NFC] Use 'profitable' rather than 'beneficial' to name method.Kai Luo1-8/+8
2019-08-01Finish moving TargetRegisterInfo::isVirtualRegister() and friends to llvm::Re...Daniel Sanders1-13/+11
2019-07-19[MachineCSE][MachinePRE] Avoid hoisting code from code regions into hot BBs.Kai Luo1-0/+25
2019-06-12[MIR] Skip hoisting to basic block which may throw exception or returnAnton Afanasyev1-0/+2
2019-06-09[MIR] Add simple PRE pass to MachineCSEAnton Afanasyev1-9/+118
2019-06-05Allow target to handle STRICT floating-point nodesUlrich Weigand1-1/+1
2019-05-27Revert r361356: "[MIR] Add simple PRE pass to MachineCSE"David L. Jones1-113/+9
2019-05-22[MIR] Add simple PRE pass to MachineCSEAnton Afanasyev1-9/+113
2019-05-03Revert "[MIR] Add simple PRE pass to MachineCSE"Anton Afanasyev1-117/+9
2019-05-03[MIR] Add simple PRE pass to MachineCSEAnton Afanasyev1-9/+117
2019-02-20[Codegen] Remove dead flags on Physical Defs in machine cseDavid Green1-19/+24
2019-01-19Update the file headers across all of the LLVM projects in the monorepoChandler Carruth1-4/+3
2018-10-20[MachineCSE][GlobalISel] Making sure MachineCSE works mid-GlobalISel (again)Roman Tereshin1-1/+16
2018-10-01[DebugInfo][Dexter] Incorrect DBG_VALUE after MCP dead copy instruction removal.Carlos Alberto Enciso1-6/+2
2018-08-30[DWARF] Missing location debug information with -O2.Carlos Alberto Enciso1-0/+8
2018-06-12[MIR][MachineCSE] Implementing proper MachineInstr::getNumExplicitDefs()Roman Tereshin1-2/+1
2018-05-14Rename DEBUG macro to LLVM_DEBUG.Nicola Zaghen1-8/+9
2018-05-09[DebugInfo] Examine all uses of isDebugValue() for debug instructions.Shiva Chen1-2/+2
2018-05-04[MachineCSE] Rewrite a loop checking if a block is in a set of blocks without...Michael Zolotukhin1-7/+5
2018-01-18GlobalISel: Make MachineCSE runnable in the middle of the GlobalISelJustin Bogner1-7/+6
2017-12-15MachineFunction: Return reference from getFunction(); NFCMatthias Braun1-1/+1
2017-12-07[CodeGen] Use MachineOperand::print in the MIRPrinter for MO_Register.Francis Visoiu Mistrih1-4/+4
2017-11-28[CodeGen] Print register names in lowercase in both MIR and debug outputFrancis Visoiu Mistrih1-5/+5
2017-11-20[MachineCSE] Add new callback for is caller preserved or constant physregsTony Jiang1-2/+2
2017-11-17Fix a bunch more layering of CodeGen headers that are in TargetDavid Blaikie1-3/+3
2017-11-08Target/TargetInstrInfo.h -> CodeGen/TargetInstrInfo.h to match layeringDavid Blaikie1-1/+1
2017-08-24[CodeGen] Fix some Clang-tidy modernize-use-using and Include What You Use wa...Eugene Zelenko1-11/+36
2017-06-06Sort the remaining #include lines in include/... and lib/....Chandler Carruth1-1/+1
2017-05-25CodeGen: Rename DEBUG_TYPE to match passnamesMatthias Braun1-4/+4
2017-05-24MachineCSE: Respect interblock physreg livenessMikael Holmen1-2/+2
2016-12-16 [codegen] Add generic functions to skip debug values.Florian Hahn1-2/+1
2016-10-28MachineRegisterInfo: Remove unused arg from isConstantPhysReg(); NFCMatthias Braun1-1/+1
2016-09-10[CodeGen] Rename MachineInstr::isInvariantLoad to isDereferenceableInvariantL...Justin Lebar1-1/+1
2016-06-30CodeGen: Use MachineInstr& in TargetInstrInfo, NFCDuncan P. N. Exon Smith1-4/+3
2016-04-22Re-commit optimization bisect support (r267022) without new pass manager supp...Andrew Kaylor1-1/+1
2016-04-22Revert "Initial implementation of optimization bisect support."Vedant Kumar1-1/+1
2016-04-21Initial implementation of optimization bisect support.Andrew Kaylor1-1/+1
2016-04-19[SSP, 2/2] Create llvm.stackguard() intrinsic and lower it to LOAD_STACK_GUARDTim Shen1-0/+6
2016-01-06rangify; NFCISanjay Patel1-24/+14
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