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| author | Mikael Holmen <mikael.holmen@ericsson.com> | 2017-05-24 09:35:23 +0000 |
|---|---|---|
| committer | Mikael Holmen <mikael.holmen@ericsson.com> | 2017-05-24 09:35:23 +0000 |
| commit | 2676f8269a1e2b4bf9b92868ecb0f3c5ebe76eb6 (patch) | |
| tree | 53e14d5a6fc22d7f0b3dc34f83a19b0268823f10 /llvm/lib/CodeGen/MachineCSE.cpp | |
| parent | 13e016bf48e811a7f852a363211ba97d7af442f6 (diff) | |
| download | llvm-2676f8269a1e2b4bf9b92868ecb0f3c5ebe76eb6.zip llvm-2676f8269a1e2b4bf9b92868ecb0f3c5ebe76eb6.tar.gz llvm-2676f8269a1e2b4bf9b92868ecb0f3c5ebe76eb6.tar.bz2 | |
MachineCSE: Respect interblock physreg liveness
Summary:
This is a fix for PR32538. MachineCSE first looks at MO.isDead(), but
if it is not marked dead, MachineCSE still wants to do its own check
to see if it is trivially dead. This check for the trivial case
assumed that physical registers cannot be live out of a block.
Patch by Mattias Eriksson.
Reviewers: qcolombet, jbhateja
Reviewed By: qcolombet, jbhateja
Subscribers: jbhateja, llvm-commits
Differential Revision: https://reviews.llvm.org/D33408
llvm-svn: 303731
Diffstat (limited to 'llvm/lib/CodeGen/MachineCSE.cpp')
| -rw-r--r-- | llvm/lib/CodeGen/MachineCSE.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/llvm/lib/CodeGen/MachineCSE.cpp b/llvm/lib/CodeGen/MachineCSE.cpp index 0766f46..5a035c7 100644 --- a/llvm/lib/CodeGen/MachineCSE.cpp +++ b/llvm/lib/CodeGen/MachineCSE.cpp @@ -180,8 +180,8 @@ MachineCSE::isPhysDefTriviallyDead(unsigned Reg, I = skipDebugInstructionsForward(I, E); if (I == E) - // Reached end of block, register is obviously dead. - return true; + // Reached end of block, we don't know if register is dead or not. + return false; bool SeenDef = false; for (const MachineOperand &MO : I->operands()) { |