diff options
Diffstat (limited to 'llvm/test/CodeGen')
112 files changed, 1686 insertions, 320 deletions
diff --git a/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir b/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir index f34d3ed..6b2a31b 100644 --- a/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir +++ b/llvm/test/CodeGen/AArch64/arm64-copy-phys-zero-reg.mir @@ -35,7 +35,7 @@ body: | ; CHECK-NOZCZ-GPR32-ZCZ-GPR64-LABEL: name: f0 ; CHECK-NOZCZ-GPR32-ZCZ-GPR64: liveins: $x0, $lr ; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: {{ $}} - ; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: $w0 = ORRWrr $wzr, $wzr + ; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: $x0 = MOVZXi 0, 0 ; CHECK-NOZCZ-GPR32-ZCZ-GPR64-NEXT: BL @f2, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit $w0, implicit-def $sp, implicit-def $w0 ; ; CHECK-ZCZ-GPR32-ZCZ-GPR64-LABEL: name: f0 diff --git a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll index dc64306..0f284aa 100644 --- a/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll +++ b/llvm/test/CodeGen/AArch64/arm64-zero-cycle-zeroing-gpr.ll @@ -1,41 +1,44 @@ -; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR +; RUN: llc < %s -mtriple=aarch64-linux-gnu | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64 ; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr32 | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32 -; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr64 | FileCheck %s -check-prefixes=ALL,ZCZ-GPR64 -; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR +; RUN: llc < %s -mtriple=aarch64-linux-gnu -mattr=+zcz-gpr64 | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-ZCZ-GPR64 +; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=generic | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64 ; RUN: llc < %s -mtriple=arm64-apple-ios -mcpu=cyclone | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64 ; RUN: llc < %s -mtriple=arm64-apple-macosx -mcpu=apple-m1 | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64 -; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR +; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=exynos-m3 | FileCheck %s -check-prefixes=ALL,NOZCZ-GPR32-NOZCZ-GPR64 ; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=kryo | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64 ; RUN: llc < %s -mtriple=aarch64-linux-gnu -mcpu=falkor | FileCheck %s -check-prefixes=ALL,ZCZ-GPR32,ZCZ-GPR64 define i8 @ti8() { entry: ; ALL-LABEL: ti8: -; NOZCZ-GPR: mov w0, wzr +; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr ; ZCZ-GPR32: mov w0, #0 +; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0 ret i8 0 } define i16 @ti16() { entry: ; ALL-LABEL: ti16: -; NOZCZ-GPR: mov w0, wzr +; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr ; ZCZ-GPR32: mov w0, #0 +; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0 ret i16 0 } define i32 @ti32() { entry: ; ALL-LABEL: ti32: -; NOZCZ-GPR: mov w0, wzr +; NOZCZ-GPR32-NOZCZ-GPR64: mov w0, wzr ; ZCZ-GPR32: mov w0, #0 +; NOZCZ-GPR32-ZCZ-GPR64: mov x0, #0 ret i32 0 } define i64 @ti64() { entry: ; ALL-LABEL: ti64: -; NOZCZ-GPR: mov x0, xzr +; NOZCZ-GPR32-NOZCZ-GPR64 mov x0, xzr ; ZCZ-GPR64: mov x0, #0 ret i64 0 } diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir index 423ce82..d5947c8 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.mir @@ -90,9 +90,7 @@ body: | ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $vgpr2_vgpr3 ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[UV]](s32) - ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[COPY]](<2 x s32>) - ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[UV2]](s32) - ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY2]](s32) ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[BUILD_VECTOR]](<2 x s32>) %0:_(<2 x s32>) = COPY $vgpr0_vgpr1 %1:_(<2 x s32>) = COPY $vgpr2_vgpr3 @@ -328,3 +326,30 @@ body: | $vgpr0_vgpr1 = COPY %4 ... + +--- +name: shufflevector_cache_element +tracksRegLiveness: true + +body: | + bb.0: + liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + + ; CHECK-LABEL: name: shufflevector_cache_element + ; CHECK: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 + ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 + ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY [[COPY]](s32) + ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY [[COPY1]](s32) + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<8 x s32>) = G_BUILD_VECTOR [[COPY2]](s32), [[COPY2]](s32), [[COPY2]](s32), [[COPY2]](s32), [[COPY3]](s32), [[COPY3]](s32), [[COPY3]](s32), [[COPY3]](s32) + ; CHECK-NEXT: [[EVEC:%[0-9]+]]:_(s32) = G_EXTRACT_VECTOR_ELT [[BUILD_VECTOR]](<8 x s32>), [[COPY1]](s32) + ; CHECK-NEXT: $vgpr0 = COPY [[EVEC]](s32) + %0:_(s32) = COPY $vgpr0 + %1:_(s32) = COPY $vgpr1 + %2:_(<2 x s32>) = G_BUILD_VECTOR %0, %1 + %3:_(<8 x s32>) = G_SHUFFLE_VECTOR %2, %2, shufflemask(0, 0, 0, 0, 3, 3, 3, 3) + %4:_(s32) = G_EXTRACT_VECTOR_ELT %3(<8 x s32>), %1(s32) + $vgpr0 = COPY %4 + +... diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir index 10f425c..dff8111 100644 --- a/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-shuffle-vector.s16.mir @@ -237,16 +237,13 @@ body: | ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) - ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) - ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]] - ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]] ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32) + ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32) ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]] - ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) - ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>) + ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) + ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) ; ; GFX9-LABEL: name: shufflevector_v2s16_v2s16_0_0 ; GFX9: liveins: $vgpr0, $vgpr1 @@ -257,10 +254,7 @@ body: | ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) - ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32) - ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) + ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC]](s16) ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) %0:_(<2 x s16>) = COPY $vgpr0 %1:_(<2 x s16>) = COPY $vgpr1 @@ -285,12 +279,10 @@ body: | ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) - ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) - ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) - ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32) + ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32) ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] - ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) - ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>) + ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) + ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) ; ; GFX9-LABEL: name: shufflevector_v2s16_v2s16_1_1 ; GFX9: liveins: $vgpr0, $vgpr1 @@ -301,10 +293,7 @@ body: | ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) - ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32) - ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) + ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC]](s16) ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) %0:_(<2 x s16>) = COPY $vgpr0 %1:_(<2 x s16>) = COPY $vgpr1 @@ -329,16 +318,13 @@ body: | ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) - ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) - ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]] - ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]] ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32) + ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32) ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]] - ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) - ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>) + ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) + ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) ; ; GFX9-LABEL: name: shufflevector_v2s16_v2s16_2_2 ; GFX9: liveins: $vgpr0, $vgpr1 @@ -349,10 +335,7 @@ body: | ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) - ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32) - ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) + ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC]](s16) ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) %0:_(<2 x s16>) = COPY $vgpr0 %1:_(<2 x s16>) = COPY $vgpr1 @@ -641,12 +624,10 @@ body: | ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) - ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) - ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) - ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR1]], [[C]](s32) + ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[LSHR]], [[C]](s32) ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[LSHR]], [[SHL]] - ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) - ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>) + ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) + ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) ; ; GFX9-LABEL: name: shufflevector_v2s16_v2s16_3_3 ; GFX9: liveins: $vgpr0, $vgpr1 @@ -657,10 +638,7 @@ body: | ; GFX9-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY1]](<2 x s16>) - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) - ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32) - ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) + ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC]](s16) ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) %0:_(<2 x s16>) = COPY $vgpr0 %1:_(<2 x s16>) = COPY $vgpr1 @@ -733,16 +711,13 @@ body: | ; GFX8-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0 ; GFX8-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX8-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) - ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) - ; GFX8-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) ; GFX8-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535 ; GFX8-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LSHR]], [[C1]] - ; GFX8-NEXT: [[AND1:%[0-9]+]]:_(s32) = G_AND [[LSHR1]], [[C1]] ; GFX8-NEXT: [[C2:%[0-9]+]]:_(s32) = G_CONSTANT i32 16 - ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND1]], [[C2]](s32) + ; GFX8-NEXT: [[SHL:%[0-9]+]]:_(s32) = G_SHL [[AND]], [[C2]](s32) ; GFX8-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[AND]], [[SHL]] - ; GFX8-NEXT: [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) - ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST2]](<2 x s16>) + ; GFX8-NEXT: [[BITCAST1:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[OR]](s32) + ; GFX8-NEXT: $vgpr0 = COPY [[BITCAST1]](<2 x s16>) ; ; GFX9-LABEL: name: shufflevector_v2s16_v2s16_2_0 ; GFX9: liveins: $vgpr0, $vgpr1 @@ -753,10 +728,7 @@ body: | ; GFX9-NEXT: [[BITCAST:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) ; GFX9-NEXT: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST]], [[C]](s32) ; GFX9-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR]](s32) - ; GFX9-NEXT: [[BITCAST1:%[0-9]+]]:_(s32) = G_BITCAST [[COPY]](<2 x s16>) - ; GFX9-NEXT: [[LSHR1:%[0-9]+]]:_(s32) = G_LSHR [[BITCAST1]], [[C]](s32) - ; GFX9-NEXT: [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[LSHR1]](s32) - ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC1]](s16) + ; GFX9-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[TRUNC]](s16), [[TRUNC]](s16) ; GFX9-NEXT: $vgpr0 = COPY [[BUILD_VECTOR]](<2 x s16>) %0:_(<2 x s16>) = COPY $vgpr0 %1:_(<2 x s16>) = COPY $vgpr1 diff --git a/llvm/test/CodeGen/ARM/load-combine-big-endian.ll b/llvm/test/CodeGen/ARM/load-combine-big-endian.ll index 4b6d14e..1d5c858 100644 --- a/llvm/test/CodeGen/ARM/load-combine-big-endian.ll +++ b/llvm/test/CodeGen/ARM/load-combine-big-endian.ll @@ -53,14 +53,12 @@ define i32 @load_i32_by_i8_bswap(ptr %arg) { ; BSWAP is not supported by 32 bit target ; CHECK-LABEL: load_i32_by_i8_bswap: ; CHECK: @ %bb.0: +; CHECK-NEXT: mov r1, #255 ; CHECK-NEXT: ldr r0, [r0] -; CHECK-NEXT: mov r1, #65280 -; CHECK-NEXT: and r2, r0, #65280 -; CHECK-NEXT: and r1, r1, r0, lsr #8 -; CHECK-NEXT: orr r1, r1, r0, lsr #24 -; CHECK-NEXT: lsl r0, r0, #24 -; CHECK-NEXT: orr r0, r0, r2, lsl #8 -; CHECK-NEXT: orr r0, r0, r1 +; CHECK-NEXT: orr r1, r1, #16711680 +; CHECK-NEXT: and r2, r0, r1 +; CHECK-NEXT: and r0, r1, r0, ror #24 +; CHECK-NEXT: orr r0, r0, r2, ror #8 ; CHECK-NEXT: mov pc, lr ; ; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap: @@ -223,21 +221,16 @@ define i32 @load_i32_by_i16_i8(ptr %arg) { define i64 @load_i64_by_i8_bswap(ptr %arg) { ; CHECK-LABEL: load_i64_by_i8_bswap: ; CHECK: @ %bb.0: +; CHECK-NEXT: mov r2, #255 ; CHECK-NEXT: ldr r1, [r0] -; CHECK-NEXT: mov r12, #65280 ; CHECK-NEXT: ldr r0, [r0, #4] -; CHECK-NEXT: and r2, r0, #65280 -; CHECK-NEXT: and r3, r12, r0, lsr #8 -; CHECK-NEXT: orr r3, r3, r0, lsr #24 -; CHECK-NEXT: lsl r0, r0, #24 -; CHECK-NEXT: orr r0, r0, r2, lsl #8 -; CHECK-NEXT: and r2, r12, r1, lsr #8 -; CHECK-NEXT: orr r0, r0, r3 -; CHECK-NEXT: and r3, r1, #65280 -; CHECK-NEXT: orr r2, r2, r1, lsr #24 -; CHECK-NEXT: lsl r1, r1, #24 -; CHECK-NEXT: orr r1, r1, r3, lsl #8 -; CHECK-NEXT: orr r1, r1, r2 +; CHECK-NEXT: orr r2, r2, #16711680 +; CHECK-NEXT: and r3, r0, r2 +; CHECK-NEXT: and r0, r2, r0, ror #24 +; CHECK-NEXT: orr r0, r0, r3, ror #8 +; CHECK-NEXT: and r3, r1, r2 +; CHECK-NEXT: and r1, r2, r1, ror #24 +; CHECK-NEXT: orr r1, r1, r3, ror #8 ; CHECK-NEXT: mov pc, lr ; ; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap: @@ -377,14 +370,12 @@ define i64 @load_i64_by_i8(ptr %arg) { define i32 @load_i32_by_i8_nonzero_offset(ptr %arg) { ; CHECK-LABEL: load_i32_by_i8_nonzero_offset: ; CHECK: @ %bb.0: +; CHECK-NEXT: mov r1, #255 ; CHECK-NEXT: ldr r0, [r0, #1] -; CHECK-NEXT: mov r1, #65280 -; CHECK-NEXT: and r2, r0, #65280 -; CHECK-NEXT: and r1, r1, r0, lsr #8 -; CHECK-NEXT: orr r1, r1, r0, lsr #24 -; CHECK-NEXT: lsl r0, r0, #24 -; CHECK-NEXT: orr r0, r0, r2, lsl #8 -; CHECK-NEXT: orr r0, r0, r1 +; CHECK-NEXT: orr r1, r1, #16711680 +; CHECK-NEXT: and r2, r0, r1 +; CHECK-NEXT: and r0, r1, r0, ror #24 +; CHECK-NEXT: orr r0, r0, r2, ror #8 ; CHECK-NEXT: mov pc, lr ; ; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset: @@ -434,14 +425,12 @@ define i32 @load_i32_by_i8_nonzero_offset(ptr %arg) { define i32 @load_i32_by_i8_neg_offset(ptr %arg) { ; CHECK-LABEL: load_i32_by_i8_neg_offset: ; CHECK: @ %bb.0: +; CHECK-NEXT: mov r1, #255 ; CHECK-NEXT: ldr r0, [r0, #-4] -; CHECK-NEXT: mov r1, #65280 -; CHECK-NEXT: and r2, r0, #65280 -; CHECK-NEXT: and r1, r1, r0, lsr #8 -; CHECK-NEXT: orr r1, r1, r0, lsr #24 -; CHECK-NEXT: lsl r0, r0, #24 -; CHECK-NEXT: orr r0, r0, r2, lsl #8 -; CHECK-NEXT: orr r0, r0, r1 +; CHECK-NEXT: orr r1, r1, #16711680 +; CHECK-NEXT: and r2, r0, r1 +; CHECK-NEXT: and r0, r1, r0, ror #24 +; CHECK-NEXT: orr r0, r0, r2, ror #8 ; CHECK-NEXT: mov pc, lr ; ; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset: @@ -587,14 +576,12 @@ declare i16 @llvm.bswap.i16(i16) define i32 @load_i32_by_bswap_i16(ptr %arg) { ; CHECK-LABEL: load_i32_by_bswap_i16: ; CHECK: @ %bb.0: +; CHECK-NEXT: mov r1, #255 ; CHECK-NEXT: ldr r0, [r0] -; CHECK-NEXT: mov r1, #65280 -; CHECK-NEXT: and r2, r0, #65280 -; CHECK-NEXT: and r1, r1, r0, lsr #8 -; CHECK-NEXT: orr r1, r1, r0, lsr #24 -; CHECK-NEXT: lsl r0, r0, #24 -; CHECK-NEXT: orr r0, r0, r2, lsl #8 -; CHECK-NEXT: orr r0, r0, r1 +; CHECK-NEXT: orr r1, r1, #16711680 +; CHECK-NEXT: and r2, r0, r1 +; CHECK-NEXT: and r0, r1, r0, ror #24 +; CHECK-NEXT: orr r0, r0, r2, ror #8 ; CHECK-NEXT: mov pc, lr ; ; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16: @@ -667,14 +654,12 @@ define i32 @load_i32_by_i8_base_offset_index(ptr %arg, i32 %i) { ; CHECK-LABEL: load_i32_by_i8_base_offset_index: ; CHECK: @ %bb.0: ; CHECK-NEXT: add r0, r0, r1 -; CHECK-NEXT: mov r1, #65280 +; CHECK-NEXT: mov r1, #255 +; CHECK-NEXT: orr r1, r1, #16711680 ; CHECK-NEXT: ldr r0, [r0, #12] -; CHECK-NEXT: and r2, r0, #65280 -; CHECK-NEXT: and r1, r1, r0, lsr #8 -; CHECK-NEXT: orr r1, r1, r0, lsr #24 -; CHECK-NEXT: lsl r0, r0, #24 -; CHECK-NEXT: orr r0, r0, r2, lsl #8 -; CHECK-NEXT: orr r0, r0, r1 +; CHECK-NEXT: and r2, r0, r1 +; CHECK-NEXT: and r0, r1, r0, ror #24 +; CHECK-NEXT: orr r0, r0, r2, ror #8 ; CHECK-NEXT: mov pc, lr ; ; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index: @@ -733,14 +718,12 @@ define i32 @load_i32_by_i8_base_offset_index_2(ptr %arg, i32 %i) { ; CHECK-LABEL: load_i32_by_i8_base_offset_index_2: ; CHECK: @ %bb.0: ; CHECK-NEXT: add r0, r1, r0 -; CHECK-NEXT: mov r1, #65280 +; CHECK-NEXT: mov r1, #255 +; CHECK-NEXT: orr r1, r1, #16711680 ; CHECK-NEXT: ldr r0, [r0, #13] -; CHECK-NEXT: and r2, r0, #65280 -; CHECK-NEXT: and r1, r1, r0, lsr #8 -; CHECK-NEXT: orr r1, r1, r0, lsr #24 -; CHECK-NEXT: lsl r0, r0, #24 -; CHECK-NEXT: orr r0, r0, r2, lsl #8 -; CHECK-NEXT: orr r0, r0, r1 +; CHECK-NEXT: and r2, r0, r1 +; CHECK-NEXT: and r0, r1, r0, ror #24 +; CHECK-NEXT: orr r0, r0, r2, ror #8 ; CHECK-NEXT: mov pc, lr ; ; CHECK-ARMv6-LABEL: load_i32_by_i8_base_offset_index_2: diff --git a/llvm/test/CodeGen/ARM/load-combine.ll b/llvm/test/CodeGen/ARM/load-combine.ll index 0f6ec8a..7087367 100644 --- a/llvm/test/CodeGen/ARM/load-combine.ll +++ b/llvm/test/CodeGen/ARM/load-combine.ll @@ -117,14 +117,12 @@ define i32 @load_i32_by_i8_bswap(ptr %arg) { ; BSWAP is not supported by 32 bit target ; CHECK-LABEL: load_i32_by_i8_bswap: ; CHECK: @ %bb.0: +; CHECK-NEXT: mov r1, #255 ; CHECK-NEXT: ldr r0, [r0] -; CHECK-NEXT: mov r1, #65280 -; CHECK-NEXT: and r2, r0, #65280 -; CHECK-NEXT: and r1, r1, r0, lsr #8 -; CHECK-NEXT: orr r1, r1, r0, lsr #24 -; CHECK-NEXT: lsl r0, r0, #24 -; CHECK-NEXT: orr r0, r0, r2, lsl #8 -; CHECK-NEXT: orr r0, r0, r1 +; CHECK-NEXT: orr r1, r1, #16711680 +; CHECK-NEXT: and r2, r0, r1 +; CHECK-NEXT: and r0, r1, r0, ror #24 +; CHECK-NEXT: orr r0, r0, r2, ror #8 ; CHECK-NEXT: mov pc, lr ; ; CHECK-ARMv6-LABEL: load_i32_by_i8_bswap: @@ -237,21 +235,16 @@ define i64 @load_i64_by_i8(ptr %arg) { define i64 @load_i64_by_i8_bswap(ptr %arg) { ; CHECK-LABEL: load_i64_by_i8_bswap: ; CHECK: @ %bb.0: +; CHECK-NEXT: mov r2, #255 ; CHECK-NEXT: ldr r1, [r0] -; CHECK-NEXT: mov r12, #65280 ; CHECK-NEXT: ldr r0, [r0, #4] -; CHECK-NEXT: and r2, r0, #65280 -; CHECK-NEXT: and r3, r12, r0, lsr #8 -; CHECK-NEXT: orr r3, r3, r0, lsr #24 -; CHECK-NEXT: lsl r0, r0, #24 -; CHECK-NEXT: orr r0, r0, r2, lsl #8 -; CHECK-NEXT: and r2, r12, r1, lsr #8 -; CHECK-NEXT: orr r0, r0, r3 -; CHECK-NEXT: and r3, r1, #65280 -; CHECK-NEXT: orr r2, r2, r1, lsr #24 -; CHECK-NEXT: lsl r1, r1, #24 -; CHECK-NEXT: orr r1, r1, r3, lsl #8 -; CHECK-NEXT: orr r1, r1, r2 +; CHECK-NEXT: orr r2, r2, #16711680 +; CHECK-NEXT: and r3, r0, r2 +; CHECK-NEXT: and r0, r2, r0, ror #24 +; CHECK-NEXT: orr r0, r0, r3, ror #8 +; CHECK-NEXT: and r3, r1, r2 +; CHECK-NEXT: and r1, r2, r1, ror #24 +; CHECK-NEXT: orr r1, r1, r3, ror #8 ; CHECK-NEXT: mov pc, lr ; ; CHECK-ARMv6-LABEL: load_i64_by_i8_bswap: @@ -413,14 +406,12 @@ define i32 @load_i32_by_i8_neg_offset(ptr %arg) { define i32 @load_i32_by_i8_nonzero_offset_bswap(ptr %arg) { ; CHECK-LABEL: load_i32_by_i8_nonzero_offset_bswap: ; CHECK: @ %bb.0: +; CHECK-NEXT: mov r1, #255 ; CHECK-NEXT: ldr r0, [r0, #1] -; CHECK-NEXT: mov r1, #65280 -; CHECK-NEXT: and r2, r0, #65280 -; CHECK-NEXT: and r1, r1, r0, lsr #8 -; CHECK-NEXT: orr r1, r1, r0, lsr #24 -; CHECK-NEXT: lsl r0, r0, #24 -; CHECK-NEXT: orr r0, r0, r2, lsl #8 -; CHECK-NEXT: orr r0, r0, r1 +; CHECK-NEXT: orr r1, r1, #16711680 +; CHECK-NEXT: and r2, r0, r1 +; CHECK-NEXT: and r0, r1, r0, ror #24 +; CHECK-NEXT: orr r0, r0, r2, ror #8 ; CHECK-NEXT: mov pc, lr ; ; CHECK-ARMv6-LABEL: load_i32_by_i8_nonzero_offset_bswap: @@ -469,14 +460,12 @@ define i32 @load_i32_by_i8_nonzero_offset_bswap(ptr %arg) { define i32 @load_i32_by_i8_neg_offset_bswap(ptr %arg) { ; CHECK-LABEL: load_i32_by_i8_neg_offset_bswap: ; CHECK: @ %bb.0: +; CHECK-NEXT: mov r1, #255 ; CHECK-NEXT: ldr r0, [r0, #-4] -; CHECK-NEXT: mov r1, #65280 -; CHECK-NEXT: and r2, r0, #65280 -; CHECK-NEXT: and r1, r1, r0, lsr #8 -; CHECK-NEXT: orr r1, r1, r0, lsr #24 -; CHECK-NEXT: lsl r0, r0, #24 -; CHECK-NEXT: orr r0, r0, r2, lsl #8 -; CHECK-NEXT: orr r0, r0, r1 +; CHECK-NEXT: orr r1, r1, #16711680 +; CHECK-NEXT: and r2, r0, r1 +; CHECK-NEXT: and r0, r1, r0, ror #24 +; CHECK-NEXT: orr r0, r0, r2, ror #8 ; CHECK-NEXT: mov pc, lr ; ; CHECK-ARMv6-LABEL: load_i32_by_i8_neg_offset_bswap: @@ -527,14 +516,12 @@ declare i16 @llvm.bswap.i16(i16) define i32 @load_i32_by_bswap_i16(ptr %arg) { ; CHECK-LABEL: load_i32_by_bswap_i16: ; CHECK: @ %bb.0: +; CHECK-NEXT: mov r1, #255 ; CHECK-NEXT: ldr r0, [r0] -; CHECK-NEXT: mov r1, #65280 -; CHECK-NEXT: and r2, r0, #65280 -; CHECK-NEXT: and r1, r1, r0, lsr #8 -; CHECK-NEXT: orr r1, r1, r0, lsr #24 -; CHECK-NEXT: lsl r0, r0, #24 -; CHECK-NEXT: orr r0, r0, r2, lsl #8 -; CHECK-NEXT: orr r0, r0, r1 +; CHECK-NEXT: orr r1, r1, #16711680 +; CHECK-NEXT: and r2, r0, r1 +; CHECK-NEXT: and r0, r1, r0, ror #24 +; CHECK-NEXT: orr r0, r0, r2, ror #8 ; CHECK-NEXT: mov pc, lr ; ; CHECK-ARMv6-LABEL: load_i32_by_bswap_i16: diff --git a/llvm/test/CodeGen/DirectX/legalize-module-flags.ll b/llvm/test/CodeGen/DirectX/legalize-module-flags.ll index 6c29dea..044bd91 100644 --- a/llvm/test/CodeGen/DirectX/legalize-module-flags.ll +++ b/llvm/test/CodeGen/DirectX/legalize-module-flags.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -dxil-prepare -mtriple=dxil-unknown-shadermodel6.0-compute %s | FileCheck %s +; RUN: opt -S -dxil-translate-metadata -mtriple=dxil-unknown-shadermodel6.0-compute %s | FileCheck %s ; Make sure behavior flag > 6 is fixed. ; CHECK: !{i32 2, !"frame-pointer", i32 2} diff --git a/llvm/test/CodeGen/DirectX/legalize-module-flags2.ll b/llvm/test/CodeGen/DirectX/legalize-module-flags2.ll index 244ec8d..b8a60a8 100644 --- a/llvm/test/CodeGen/DirectX/legalize-module-flags2.ll +++ b/llvm/test/CodeGen/DirectX/legalize-module-flags2.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -dxil-prepare -mtriple=dxil-unknown-shadermodel6.0-library %s | FileCheck %s +; RUN: opt -S -dxil-translate-metadata -mtriple=dxil-unknown-shadermodel6.0-library %s | FileCheck %s ; CHECK: define void @main() ; Make sure behavior flag > 6 is fixed. diff --git a/llvm/test/CodeGen/DirectX/llc-pipeline.ll b/llvm/test/CodeGen/DirectX/llc-pipeline.ll index 13c2539..d265826 100644 --- a/llvm/test/CodeGen/DirectX/llc-pipeline.ll +++ b/llvm/test/CodeGen/DirectX/llc-pipeline.ll @@ -40,8 +40,8 @@ ; CHECK-NEXT: DXIL Resources Analysis ; CHECK-NEXT: DXIL Module Metadata analysis ; CHECK-NEXT: DXIL Shader Flag Analysis -; CHECK-NEXT: DXIL Translate Metadata ; CHECK-NEXT: DXIL Root Signature Analysis +; CHECK-NEXT: DXIL Translate Metadata ; CHECK-NEXT: DXIL Post Optimization Validation ; CHECK-NEXT: DXIL Op Lowering ; CHECK-NEXT: DXIL Prepare Module diff --git a/llvm/test/CodeGen/DirectX/metadata-stripping.ll b/llvm/test/CodeGen/DirectX/metadata-stripping.ll index eb939ba..531ab6c 100644 --- a/llvm/test/CodeGen/DirectX/metadata-stripping.ll +++ b/llvm/test/CodeGen/DirectX/metadata-stripping.ll @@ -1,4 +1,4 @@ -; RUN: opt -S --dxil-prepare %s | FileCheck %s +; RUN: opt -S --dxil-translate-metadata %s | FileCheck %s ; Test that only metadata nodes that are valid in DXIL are allowed through diff --git a/llvm/test/CodeGen/DirectX/strip-llvm-errno-tbaa.ll b/llvm/test/CodeGen/DirectX/strip-llvm-errno-tbaa.ll index 9190d03..2c4140d 100644 --- a/llvm/test/CodeGen/DirectX/strip-llvm-errno-tbaa.ll +++ b/llvm/test/CodeGen/DirectX/strip-llvm-errno-tbaa.ll @@ -1,6 +1,6 @@ -; RUN: opt -S -dxil-prepare < %s | FileCheck %s +; RUN: opt -S -dxil-translate-metadata < %s | FileCheck %s -; Ensures that dxil-prepare will remove the llvm.errno.tbaa metadata +; Ensures that dxil-translate-metadata will remove the llvm.errno.tbaa metadata target triple = "dxil-unknown-shadermodel6.0-compute" @@ -10,7 +10,6 @@ entry: } ; CHECK-NOT: !llvm.errno.tbaa -; CHECK-NOT: {{^!}} !llvm.errno.tbaa = !{!0} diff --git a/llvm/test/CodeGen/DirectX/strip-rootsignatures.ll b/llvm/test/CodeGen/DirectX/strip-rootsignatures.ll index 3ac617a..daf20bf 100644 --- a/llvm/test/CodeGen/DirectX/strip-rootsignatures.ll +++ b/llvm/test/CodeGen/DirectX/strip-rootsignatures.ll @@ -1,6 +1,6 @@ -; RUN: opt -S -dxil-prepare < %s | FileCheck %s +; RUN: opt -S -dxil-translate-metadata < %s | FileCheck %s -; Ensures that dxil-prepare will remove the dx.rootsignatures metadata +; Ensures that dxil-translate-metadata will remove the dx.rootsignatures metadata target triple = "dxil-unknown-shadermodel6.0-compute" @@ -10,7 +10,6 @@ entry: } ; CHECK-NOT: !dx.rootsignatures -; CHECK-NOT: {{^!}} !dx.rootsignatures = !{!2} ; list of function/root signature pairs !2 = !{ ptr @main, !3, i32 2 } ; function, root signature diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll index b5bdf84..9630dab 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/br1.ll @@ -31,4 +31,4 @@ if.end: ; preds = %entry, %if.then } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll b/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll index a5c1cec0..d3d2e8b 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/loadstore2.ll @@ -80,6 +80,6 @@ entry: ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll b/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll index bc6f2c5..e685465 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/loadstrconst.ll @@ -17,5 +17,5 @@ entry: } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll b/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll index 90db1fd..f3b902b 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/logopm.ll @@ -590,8 +590,8 @@ entry: ret void } -attributes #0 = { noinline nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noinline nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #2 = { nounwind } !llvm.module.flags = !{!0} diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll index d1a0574..eca0d16 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorefp1.ll @@ -51,4 +51,4 @@ entry: ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll index ee174dd..33b4ef8 100644 --- a/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll +++ b/llvm/test/CodeGen/Mips/Fast-ISel/simplestorei.ll @@ -63,6 +63,6 @@ entry: ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/beqzc.ll b/llvm/test/CodeGen/Mips/beqzc.ll index 28f3f8c..42eb392 100644 --- a/llvm/test/CodeGen/Mips/beqzc.ll +++ b/llvm/test/CodeGen/Mips/beqzc.ll @@ -14,7 +14,7 @@ entry: ret i32 0 } -attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } diff --git a/llvm/test/CodeGen/Mips/beqzc1.ll b/llvm/test/CodeGen/Mips/beqzc1.ll index 915f34e..01bb5f1 100644 --- a/llvm/test/CodeGen/Mips/beqzc1.ll +++ b/llvm/test/CodeGen/Mips/beqzc1.ll @@ -19,6 +19,6 @@ if.end: ; preds = %if.then, %entry ret i32 0 } -attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } diff --git a/llvm/test/CodeGen/Mips/brsize3.ll b/llvm/test/CodeGen/Mips/brsize3.ll index 1aea201..20aab184 100644 --- a/llvm/test/CodeGen/Mips/brsize3.ll +++ b/llvm/test/CodeGen/Mips/brsize3.ll @@ -33,7 +33,7 @@ x: ; preds = %x, %entry } -attributes #0 = { noreturn nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { noreturn nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } attributes #1 = { nounwind } !1 = !{i32 45} diff --git a/llvm/test/CodeGen/Mips/brsize3a.ll b/llvm/test/CodeGen/Mips/brsize3a.ll index de866f2..b1ebbd8 100644 --- a/llvm/test/CodeGen/Mips/brsize3a.ll +++ b/llvm/test/CodeGen/Mips/brsize3a.ll @@ -20,7 +20,7 @@ x: ; preds = %x, %entry } -attributes #0 = { noreturn nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { noreturn nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } attributes #1 = { nounwind } !1 = !{i32 45} diff --git a/llvm/test/CodeGen/Mips/ci2.ll b/llvm/test/CodeGen/Mips/ci2.ll index a949729..4901d8d 100644 --- a/llvm/test/CodeGen/Mips/ci2.ll +++ b/llvm/test/CodeGen/Mips/ci2.ll @@ -33,7 +33,7 @@ if.end: ; preds = %if.else, %if.then ; constisle .4byte 305419896 # 0x12345678 } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #1 = { nounwind } !1 = !{i32 103} diff --git a/llvm/test/CodeGen/Mips/cmplarge.ll b/llvm/test/CodeGen/Mips/cmplarge.ll index db7f37a..bfb6080 100644 --- a/llvm/test/CodeGen/Mips/cmplarge.ll +++ b/llvm/test/CodeGen/Mips/cmplarge.ll @@ -33,6 +33,6 @@ for.end: ; preds = %for.body, %entry ; cmp16: .end getSubImagesLuma declare i32 @iClip3(...) #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/Mips/const1.ll b/llvm/test/CodeGen/Mips/const1.ll index 750912d..7915d66 100644 --- a/llvm/test/CodeGen/Mips/const1.ll +++ b/llvm/test/CodeGen/Mips/const1.ll @@ -28,7 +28,7 @@ entry: ; CHECK: .4byte 262991277 } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/Mips/const4a.ll b/llvm/test/CodeGen/Mips/const4a.ll index 245abbf..e88ffd3 100644 --- a/llvm/test/CodeGen/Mips/const4a.ll +++ b/llvm/test/CodeGen/Mips/const4a.ll @@ -172,8 +172,8 @@ declare void @goo(...) #1 declare void @hoo(...) #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } -attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/Mips/const6.ll b/llvm/test/CodeGen/Mips/const6.ll index f40eeef..480a958 100644 --- a/llvm/test/CodeGen/Mips/const6.ll +++ b/llvm/test/CodeGen/Mips/const6.ll @@ -154,8 +154,8 @@ entry: declare void @hoo(...) #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } -attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/Mips/const6a.ll b/llvm/test/CodeGen/Mips/const6a.ll index 720edd3a..eb62e27 100644 --- a/llvm/test/CodeGen/Mips/const6a.ll +++ b/llvm/test/CodeGen/Mips/const6a.ll @@ -23,7 +23,7 @@ entry: ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } attributes #1 = { nounwind } !1 = !{i32 121} diff --git a/llvm/test/CodeGen/Mips/ctlz.ll b/llvm/test/CodeGen/Mips/ctlz.ll index 3cc1569..49eb36f 100644 --- a/llvm/test/CodeGen/Mips/ctlz.ll +++ b/llvm/test/CodeGen/Mips/ctlz.ll @@ -22,6 +22,6 @@ declare i32 @llvm.ctlz.i32(i32, i1) #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } attributes #1 = { nounwind readnone } diff --git a/llvm/test/CodeGen/Mips/delay-slot-fill-forward.ll b/llvm/test/CodeGen/Mips/delay-slot-fill-forward.ll index 7c41641..43fd36b 100644 --- a/llvm/test/CodeGen/Mips/delay-slot-fill-forward.ll +++ b/llvm/test/CodeGen/Mips/delay-slot-fill-forward.ll @@ -161,7 +161,7 @@ if.end461: ; preds = %if.end436, %for.bod ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="mips32r2" "target-features"="+mips32r2,+nooddspreg,+fpxx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="mips32r2" "target-features"="+mips32r2,+nooddspreg,+fpxx" "use-soft-float"="false" } attributes #1 = { nounwind } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/Mips/f16abs.ll b/llvm/test/CodeGen/Mips/f16abs.ll index 23bf402..242d8ff 100644 --- a/llvm/test/CodeGen/Mips/f16abs.ll +++ b/llvm/test/CodeGen/Mips/f16abs.ll @@ -29,8 +29,8 @@ declare double @fabs(double) #1 declare float @fabsf(float) #1 -attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } -attributes #1 = { nounwind optsize readnone "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } +attributes #1 = { nounwind optsize readnone "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } attributes #2 = { nounwind optsize readnone } diff --git a/llvm/test/CodeGen/Mips/fp16instrinsmc.ll b/llvm/test/CodeGen/Mips/fp16instrinsmc.ll index 6c29c08..1582605 100644 --- a/llvm/test/CodeGen/Mips/fp16instrinsmc.ll +++ b/llvm/test/CodeGen/Mips/fp16instrinsmc.ll @@ -385,7 +385,7 @@ entry: ; Function Attrs: nounwind declare double @exp2(double) #0 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind readnone "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #1 = { nounwind readnone "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } attributes #2 = { nounwind readnone } attributes #3 = { nounwind } diff --git a/llvm/test/CodeGen/Mips/fpneeded.ll b/llvm/test/CodeGen/Mips/fpneeded.ll index cc82f81..babfcad 100644 --- a/llvm/test/CodeGen/Mips/fpneeded.ll +++ b/llvm/test/CodeGen/Mips/fpneeded.ll @@ -131,7 +131,7 @@ entry: ; 32: .set reorder ; 32: .end foo3 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } define void @vv() #0 { entry: diff --git a/llvm/test/CodeGen/Mips/fpnotneeded.ll b/llvm/test/CodeGen/Mips/fpnotneeded.ll index 761ef30..2b98f7e 100644 --- a/llvm/test/CodeGen/Mips/fpnotneeded.ll +++ b/llvm/test/CodeGen/Mips/fpnotneeded.ll @@ -61,7 +61,7 @@ entry: ; cisle: .end foo -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } define float @fv() #0 { diff --git a/llvm/test/CodeGen/Mips/hf16call32.ll b/llvm/test/CodeGen/Mips/hf16call32.ll index e187b76..33353b6 100644 --- a/llvm/test/CodeGen/Mips/hf16call32.ll +++ b/llvm/test/CodeGen/Mips/hf16call32.ll @@ -1026,5 +1026,5 @@ declare { double, double } @dc_sf(float) #1 ; stel: jr $18 ; stel: .end __call_stub_fp_dc_sf -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/hf16call32_body.ll b/llvm/test/CodeGen/Mips/hf16call32_body.ll index 3bcb6f6..2eea4c3 100644 --- a/llvm/test/CodeGen/Mips/hf16call32_body.ll +++ b/llvm/test/CodeGen/Mips/hf16call32_body.ll @@ -303,4 +303,4 @@ entry: ; stel: $__fn_local_sf_df_df = sf_df_df ; stel: .end __fn_stub_sf_df_df -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/hfptrcall.ll b/llvm/test/CodeGen/Mips/hfptrcall.ll index 920c694..2babc67 100644 --- a/llvm/test/CodeGen/Mips/hfptrcall.ll +++ b/llvm/test/CodeGen/Mips/hfptrcall.ll @@ -118,8 +118,8 @@ entry: declare i32 @printf(ptr, ...) #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/l3mc.ll b/llvm/test/CodeGen/Mips/l3mc.ll index 440da3a..dc68eaf 100644 --- a/llvm/test/CodeGen/Mips/l3mc.ll +++ b/llvm/test/CodeGen/Mips/l3mc.ll @@ -99,7 +99,7 @@ entry: ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } ; __call_stub_fp___fixunsdfsi: __call_stub_fp___fixunsdfsi: ; __call_stub_fp___floatdidf: __call_stub_fp___floatdidf: diff --git a/llvm/test/CodeGen/Mips/lcb2.ll b/llvm/test/CodeGen/Mips/lcb2.ll index 036de38..79f4b43 100644 --- a/llvm/test/CodeGen/Mips/lcb2.ll +++ b/llvm/test/CodeGen/Mips/lcb2.ll @@ -115,7 +115,7 @@ if.end: ; preds = %if.then, %entry ; lcb: .end btz ; lcbn: .end btz -attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #1 = { nounwind } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/Mips/lcb3c.ll b/llvm/test/CodeGen/Mips/lcb3c.ll index 40912f3..dd88924 100644 --- a/llvm/test/CodeGen/Mips/lcb3c.ll +++ b/llvm/test/CodeGen/Mips/lcb3c.ll @@ -51,7 +51,7 @@ if.end: ; preds = %if.else, %if.then ; lcb: jal $BB1_2 # branch ; lcb: $BB1_1: # %if.then -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/Mips/lcb4a.ll b/llvm/test/CodeGen/Mips/lcb4a.ll index a0258b1..ad843bb 100644 --- a/llvm/test/CodeGen/Mips/lcb4a.ll +++ b/llvm/test/CodeGen/Mips/lcb4a.ll @@ -55,7 +55,7 @@ if.end: ; preds = %if.else, %if.then ; ci: nop ; ci: $BB1_1: # %if.else -attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/Mips/lcb5.ll b/llvm/test/CodeGen/Mips/lcb5.ll index 22baeba..0d479ff 100644 --- a/llvm/test/CodeGen/Mips/lcb5.ll +++ b/llvm/test/CodeGen/Mips/lcb5.ll @@ -216,7 +216,7 @@ if.end: ; preds = %if.then, %entry ; ci: .p2align 2 ; ci: .end z4 -attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/Mips/mbrsize4a.ll b/llvm/test/CodeGen/Mips/mbrsize4a.ll index b8d2e2d..e6c620a 100644 --- a/llvm/test/CodeGen/Mips/mbrsize4a.ll +++ b/llvm/test/CodeGen/Mips/mbrsize4a.ll @@ -30,8 +30,8 @@ declare i32 @foo(...) #1 declare i32 @printf(ptr, ...) #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #2 = { nounwind } !1 = !{i32 68} diff --git a/llvm/test/CodeGen/Mips/micromips-attr.ll b/llvm/test/CodeGen/Mips/micromips-attr.ll index 8e70cc6..1915f3b 100644 --- a/llvm/test/CodeGen/Mips/micromips-attr.ll +++ b/llvm/test/CodeGen/Mips/micromips-attr.ll @@ -24,7 +24,7 @@ attributes #0 = { "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" - "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" + "stack-protector-buffer-size"="8" "use-soft-float"="false" } @@ -34,6 +34,6 @@ attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" - "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" + "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll b/llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll index 80294b5..eaa39e9 100644 --- a/llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll +++ b/llvm/test/CodeGen/Mips/mips16-hf-attr-2.ll @@ -28,18 +28,18 @@ attributes #0 = { "less-precise-fpmad"="false" "frame-pointer"="all" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" - "unsafe-fp-math"="false" "use-soft-float"="false" + "use-soft-float"="false" } attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" - "unsafe-fp-math"="false" "use-soft-float"="true" + "use-soft-float"="true" } attributes #2 = { "less-precise-fpmad"="false" "frame-pointer"="all" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" - "unsafe-fp-math"="false" "use-soft-float"="true" + "use-soft-float"="true" } diff --git a/llvm/test/CodeGen/Mips/mips16-hf-attr.ll b/llvm/test/CodeGen/Mips/mips16-hf-attr.ll index c8af712..cafa2d5 100644 --- a/llvm/test/CodeGen/Mips/mips16-hf-attr.ll +++ b/llvm/test/CodeGen/Mips/mips16-hf-attr.ll @@ -28,18 +28,18 @@ attributes #0 = { "less-precise-fpmad"="false" "frame-pointer"="all" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" - "unsafe-fp-math"="false" "use-soft-float"="false" + "use-soft-float"="false" } attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" - "unsafe-fp-math"="false" "use-soft-float"="true" + "use-soft-float"="true" } attributes #2 = { "less-precise-fpmad"="false" "frame-pointer"="all" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" - "unsafe-fp-math"="false" "use-soft-float"="true" + "use-soft-float"="true" } diff --git a/llvm/test/CodeGen/Mips/mips16_32_1.ll b/llvm/test/CodeGen/Mips/mips16_32_1.ll index 0d02022..963fb58 100644 --- a/llvm/test/CodeGen/Mips/mips16_32_1.ll +++ b/llvm/test/CodeGen/Mips/mips16_32_1.ll @@ -10,4 +10,4 @@ entry: ; CHECK: .ent foo ; CHECK: jrc $ra ; CHECK: .end foo -attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/mips16_32_10.ll b/llvm/test/CodeGen/Mips/mips16_32_10.ll index 86378ff..e0d6859 100644 --- a/llvm/test/CodeGen/Mips/mips16_32_10.ll +++ b/llvm/test/CodeGen/Mips/mips16_32_10.ll @@ -53,6 +53,6 @@ entry: -attributes #0 = { nounwind "less-precise-fpmad"="false" "nomips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { nounwind "less-precise-fpmad"="false" "nomips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "nomips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind "less-precise-fpmad"="false" "nomips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/mips16_32_3.ll b/llvm/test/CodeGen/Mips/mips16_32_3.ll index ee33abc..dc2fe29 100644 --- a/llvm/test/CodeGen/Mips/mips16_32_3.ll +++ b/llvm/test/CodeGen/Mips/mips16_32_3.ll @@ -62,6 +62,6 @@ entry: ; 32: .set reorder ; 32: .end main -attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "use-soft-float"="false" } +attributes #2 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/mips16_32_4.ll b/llvm/test/CodeGen/Mips/mips16_32_4.ll index da926342..2fed74d 100644 --- a/llvm/test/CodeGen/Mips/mips16_32_4.ll +++ b/llvm/test/CodeGen/Mips/mips16_32_4.ll @@ -56,6 +56,6 @@ entry: ; 32: .end main -attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "use-soft-float"="false" } +attributes #2 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/mips16_32_5.ll b/llvm/test/CodeGen/Mips/mips16_32_5.ll index 6692460..2bbe778 100644 --- a/llvm/test/CodeGen/Mips/mips16_32_5.ll +++ b/llvm/test/CodeGen/Mips/mips16_32_5.ll @@ -73,6 +73,6 @@ entry: -attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { nounwind "less-precise-fpmad"="false" "nomips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "use-soft-float"="false" } +attributes #2 = { nounwind "less-precise-fpmad"="false" "nomips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/mips16_32_6.ll b/llvm/test/CodeGen/Mips/mips16_32_6.ll index 5a464a2..0503b3f 100644 --- a/llvm/test/CodeGen/Mips/mips16_32_6.ll +++ b/llvm/test/CodeGen/Mips/mips16_32_6.ll @@ -80,6 +80,6 @@ entry: -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { nounwind "less-precise-fpmad"="false" "nomips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "use-soft-float"="false" } +attributes #2 = { nounwind "less-precise-fpmad"="false" "nomips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/mips16_32_7.ll b/llvm/test/CodeGen/Mips/mips16_32_7.ll index 236f791..2b2dd8b 100644 --- a/llvm/test/CodeGen/Mips/mips16_32_7.ll +++ b/llvm/test/CodeGen/Mips/mips16_32_7.ll @@ -68,6 +68,6 @@ entry: -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "use-soft-float"="false" } +attributes #2 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/mips16_32_8.ll b/llvm/test/CodeGen/Mips/mips16_32_8.ll index 5c0cd32..1aff91c 100644 --- a/llvm/test/CodeGen/Mips/mips16_32_8.ll +++ b/llvm/test/CodeGen/Mips/mips16_32_8.ll @@ -67,7 +67,7 @@ entry: ; 32: .set reorder ; 32: .end main -attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #3 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "use-soft-float"="false" } +attributes #2 = { "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #3 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/mips16_32_9.ll b/llvm/test/CodeGen/Mips/mips16_32_9.ll index 609f054..82d7727 100644 --- a/llvm/test/CodeGen/Mips/mips16_32_9.ll +++ b/llvm/test/CodeGen/Mips/mips16_32_9.ll @@ -44,6 +44,6 @@ entry: -attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #2 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/nomips16.ll b/llvm/test/CodeGen/Mips/nomips16.ll index 62564f9..6b51eb9 100644 --- a/llvm/test/CodeGen/Mips/nomips16.ll +++ b/llvm/test/CodeGen/Mips/nomips16.ll @@ -33,6 +33,6 @@ entry: ; CHECK: .end nofoo -attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "mips16" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "nomips16" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll b/llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll index 63a730c..a8eab07 100644 --- a/llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll +++ b/llvm/test/CodeGen/Mips/pbqp-reserved-physreg.ll @@ -31,5 +31,5 @@ bb35: ; preds = %bb unreachable } -attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="generic" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/powif64_16.ll b/llvm/test/CodeGen/Mips/powif64_16.ll index 3443b62..914ef94 100644 --- a/llvm/test/CodeGen/Mips/powif64_16.ll +++ b/llvm/test/CodeGen/Mips/powif64_16.ll @@ -17,7 +17,7 @@ define double @foo_pow_f64(double %y, i32 %p) { ret double %1 } -attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } attributes #1 = { nounwind readonly } !0 = !{!"double", !1} diff --git a/llvm/test/CodeGen/Mips/s2rem.ll b/llvm/test/CodeGen/Mips/s2rem.ll index fdf06ce..5d324cb 100644 --- a/llvm/test/CodeGen/Mips/s2rem.ll +++ b/llvm/test/CodeGen/Mips/s2rem.ll @@ -86,7 +86,7 @@ entry: declare void @vf(float) #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/sel1c.ll b/llvm/test/CodeGen/Mips/sel1c.ll index 071f988..2aaf56d 100644 --- a/llvm/test/CodeGen/Mips/sel1c.ll +++ b/llvm/test/CodeGen/Mips/sel1c.ll @@ -16,6 +16,6 @@ entry: ; cond-b-short: bteqz $BB0_{{[0-9]+}} # 16 bit inst } -attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } diff --git a/llvm/test/CodeGen/Mips/sel2c.ll b/llvm/test/CodeGen/Mips/sel2c.ll index 0c3b957..44de4ac9 100644 --- a/llvm/test/CodeGen/Mips/sel2c.ll +++ b/llvm/test/CodeGen/Mips/sel2c.ll @@ -16,6 +16,6 @@ entry: ret void } -attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } diff --git a/llvm/test/CodeGen/Mips/simplebr.ll b/llvm/test/CodeGen/Mips/simplebr.ll index cfe547f..ae09d85 100644 --- a/llvm/test/CodeGen/Mips/simplebr.ll +++ b/llvm/test/CodeGen/Mips/simplebr.ll @@ -31,7 +31,7 @@ declare void @goo(...) #1 declare void @hoo(...) #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } -attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="true" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="true" } diff --git a/llvm/test/CodeGen/Mips/sr1.ll b/llvm/test/CodeGen/Mips/sr1.ll index c6fa9fc..6c42d45 100644 --- a/llvm/test/CodeGen/Mips/sr1.ll +++ b/llvm/test/CodeGen/Mips/sr1.ll @@ -50,7 +50,7 @@ entry: declare float @xf() #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/Mips/tnaked.ll b/llvm/test/CodeGen/Mips/tnaked.ll index ac54f2f..287c009 100644 --- a/llvm/test/CodeGen/Mips/tnaked.ll +++ b/llvm/test/CodeGen/Mips/tnaked.ll @@ -25,5 +25,5 @@ entry: ; CHECK: .fmask 0x00000000,0 ; CHECK: addiu $sp, $sp, -8 -attributes #0 = { naked noinline nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { naked noinline nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir b/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir index 7d80c02..41f7599 100644 --- a/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir +++ b/llvm/test/CodeGen/PowerPC/DisableHoistingDueToBlockHotnessProfileData.mir @@ -70,7 +70,7 @@ ; Function Attrs: nounwind declare void @llvm.stackprotector(ptr, ptr) #1 - attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "use-soft-float"="false" } attributes #1 = { nounwind } !llvm.module.flags = !{!0, !1} diff --git a/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir b/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir index 60a399d..00ae719 100644 --- a/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir +++ b/llvm/test/CodeGen/PowerPC/NoCRFieldRedefWhenSpillingCRBIT.mir @@ -36,7 +36,7 @@ ; Function Attrs: nounwind declare void @llvm.stackprotector(ptr, ptr) #1 - attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #1 = { nounwind } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/PowerPC/aantidep-inline-asm-use.ll b/llvm/test/CodeGen/PowerPC/aantidep-inline-asm-use.ll index e61d51f..7e47129 100644 --- a/llvm/test/CodeGen/PowerPC/aantidep-inline-asm-use.ll +++ b/llvm/test/CodeGen/PowerPC/aantidep-inline-asm-use.ll @@ -298,7 +298,7 @@ _ZN10SubProcess12SafeSyscalls5fcntlEiil.exit: ; preds = %_ZN10SubProcess12Sa ; Function Attrs: nounwind argmemonly declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) #1 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr8" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr8" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "use-soft-float"="false" } attributes #1 = { nounwind argmemonly } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/PowerPC/addrfuncstr.ll b/llvm/test/CodeGen/PowerPC/addrfuncstr.ll index 1dbf420..473d669 100644 --- a/llvm/test/CodeGen/PowerPC/addrfuncstr.ll +++ b/llvm/test/CodeGen/PowerPC/addrfuncstr.ll @@ -23,5 +23,5 @@ declare i64 @fread(ptr, i64, i64, ptr) #1 ; CHECK: .section .data.rel.ro ; CHECK: .quad fread -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/PowerPC/asm-constraints.ll b/llvm/test/CodeGen/PowerPC/asm-constraints.ll index 9a37ba2..6c740e1 100644 --- a/llvm/test/CodeGen/PowerPC/asm-constraints.ll +++ b/llvm/test/CodeGen/PowerPC/asm-constraints.ll @@ -65,7 +65,7 @@ entry: } -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "use-soft-float"="false" } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/PowerPC/asym-regclass-copy.ll b/llvm/test/CodeGen/PowerPC/asym-regclass-copy.ll index d6b398e..6871638 100644 --- a/llvm/test/CodeGen/PowerPC/asym-regclass-copy.ll +++ b/llvm/test/CodeGen/PowerPC/asym-regclass-copy.ll @@ -52,5 +52,5 @@ declare void @free(ptr nocapture) #0 declare i64 @strtol(ptr, ptr nocapture, i32 signext) #0 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir index fac09d2..f8d32cc 100644 --- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir +++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-R0-special-handling.mir @@ -63,8 +63,8 @@ ret i64 %2 } - attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "unsafe-fp-math"="false" "use-soft-float"="false" } - attributes #1 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "use-soft-float"="false" } + attributes #1 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "use-soft-float"="false" } !llvm.module.flags = !{!0, !1} !llvm.ident = !{!2} diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir index 0b61455..72f9b02 100644 --- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir +++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs-out-of-range.mir @@ -187,7 +187,7 @@ ret i64 %cond } - attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx" "use-soft-float"="false" } !llvm.module.flags = !{!0, !1} !llvm.ident = !{!2} diff --git a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir index 61c0da6..02a3f34 100644 --- a/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir +++ b/llvm/test/CodeGen/PowerPC/convert-rr-to-ri-instrs.mir @@ -983,10 +983,10 @@ ret i64 %xor } - attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx" "unsafe-fp-math"="false" "use-soft-float"="false" } - attributes #1 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx" "unsafe-fp-math"="false" "use-soft-float"="false" } - attributes #2 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,-vsx" "unsafe-fp-math"="false" "use-soft-float"="false" } - attributes #3 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx" "use-soft-float"="false" } + attributes #1 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx" "use-soft-float"="false" } + attributes #2 = { norecurse nounwind readonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,-vsx" "use-soft-float"="false" } + attributes #3 = { norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx" "use-soft-float"="false" } !llvm.module.flags = !{!0, !1} !llvm.ident = !{!2} diff --git a/llvm/test/CodeGen/PowerPC/cr-spills.ll b/llvm/test/CodeGen/PowerPC/cr-spills.ll index 6703de6..3488fac 100644 --- a/llvm/test/CodeGen/PowerPC/cr-spills.ll +++ b/llvm/test/CodeGen/PowerPC/cr-spills.ll @@ -400,5 +400,5 @@ for.end999: ; preds = %for.inc997 ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/PowerPC/crypto_bifs.ll b/llvm/test/CodeGen/PowerPC/crypto_bifs.ll index f61c62f..9ae02c6 100644 --- a/llvm/test/CodeGen/PowerPC/crypto_bifs.ll +++ b/llvm/test/CodeGen/PowerPC/crypto_bifs.ll @@ -276,7 +276,7 @@ entry: ; Function Attrs: nounwind readnone declare <2 x i64> @llvm.ppc.altivec.crypto.vshasigmad(<2 x i64>, i32, i32) #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #1 = { nounwind readnone } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/PowerPC/ctr-cleanup.ll b/llvm/test/CodeGen/PowerPC/ctr-cleanup.ll index 9e13b6f..f7a7641 100644 --- a/llvm/test/CodeGen/PowerPC/ctr-cleanup.ll +++ b/llvm/test/CodeGen/PowerPC/ctr-cleanup.ll @@ -22,4 +22,4 @@ for.end: ; preds = %for.body, %entry ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/PowerPC/ctrloop-do-not-duplicate-mi.mir b/llvm/test/CodeGen/PowerPC/ctrloop-do-not-duplicate-mi.mir index 668e7fe..9230c31 100644 --- a/llvm/test/CodeGen/PowerPC/ctrloop-do-not-duplicate-mi.mir +++ b/llvm/test/CodeGen/PowerPC/ctrloop-do-not-duplicate-mi.mir @@ -5,7 +5,7 @@ target datalayout = "e-m:e-i64:64-n32:64-S128-v256:256:256-v512:512:512" target triple = "powerpc64le-unknown-linux-gnu" - define dso_local void @test() local_unnamed_addr #0 { + define dso_local void @test() local_unnamed_addr { test_entry: %_val_domain_ = load i32, ptr undef, align 4 %_conv765 = sext i32 %_val_domain_ to i64 @@ -53,7 +53,6 @@ ; Function Attrs: nocallback noduplicate nofree nosync nounwind willreturn declare i1 @llvm.loop.decrement.i64(i64) #2 - attributes #0 = { "unsafe-fp-math"="true" } attributes #1 = { nocallback nofree nosync nounwind readnone speculatable willreturn } attributes #2 = { nocallback noduplicate nofree nosync nounwind willreturn } diff --git a/llvm/test/CodeGen/PowerPC/ctrloop-intrin.ll b/llvm/test/CodeGen/PowerPC/ctrloop-intrin.ll index 072cefa..c9a955fb 100644 --- a/llvm/test/CodeGen/PowerPC/ctrloop-intrin.ll +++ b/llvm/test/CodeGen/PowerPC/ctrloop-intrin.ll @@ -329,7 +329,7 @@ declare void @llvm.set.loop.iterations.i64(i64) #0 declare i1 @llvm.loop.decrement(i64) #0 attributes #0 = { nounwind } -attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #2 = { nounwind } attributes #3 = { nounwind } diff --git a/llvm/test/CodeGen/PowerPC/div-e-32.ll b/llvm/test/CodeGen/PowerPC/div-e-32.ll index fe64abb..1b39d45 100644 --- a/llvm/test/CodeGen/PowerPC/div-e-32.ll +++ b/llvm/test/CodeGen/PowerPC/div-e-32.ll @@ -23,7 +23,7 @@ entry: ; Function Attrs: nounwind readnone declare i32 @llvm.ppc.divweu(i32, i32) #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #1 = { nounwind readnone } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/PowerPC/div-e-all.ll b/llvm/test/CodeGen/PowerPC/div-e-all.ll index 462086b..0728760 100644 --- a/llvm/test/CodeGen/PowerPC/div-e-all.ll +++ b/llvm/test/CodeGen/PowerPC/div-e-all.ll @@ -46,7 +46,7 @@ entry: ; Function Attrs: nounwind readnone declare i64 @llvm.ppc.divdeu(i64, i64) #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #1 = { nounwind readnone } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/PowerPC/extra-toc-reg-deps.ll b/llvm/test/CodeGen/PowerPC/extra-toc-reg-deps.ll index 00d170f..9bc8b23 100644 --- a/llvm/test/CodeGen/PowerPC/extra-toc-reg-deps.ll +++ b/llvm/test/CodeGen/PowerPC/extra-toc-reg-deps.ll @@ -419,8 +419,8 @@ declare void @_ZN4Foam11regIOobjectD2Ev() #0 declare void @_ZN4Foam6reduceIiNS_5sumOpIiEEEEvRKNS_4ListINS_8UPstream11commsStructEEERT_RKT0_ii() #0 -attributes #0 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { inlinehint "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #1 = { inlinehint "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } !llvm.module.flags = !{!0} diff --git a/llvm/test/CodeGen/PowerPC/fma-mutate-duplicate-vreg.ll b/llvm/test/CodeGen/PowerPC/fma-mutate-duplicate-vreg.ll index a336fc7..2d34e83 100644 --- a/llvm/test/CodeGen/PowerPC/fma-mutate-duplicate-vreg.ll +++ b/llvm/test/CodeGen/PowerPC/fma-mutate-duplicate-vreg.ll @@ -33,4 +33,4 @@ define float @f(float %xf) #0 { ret float %25 } -attributes #0 = { norecurse nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr8" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind readnone "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr8" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/PowerPC/frameaddr.ll b/llvm/test/CodeGen/PowerPC/frameaddr.ll index 180f736..60eb086 100644 --- a/llvm/test/CodeGen/PowerPC/frameaddr.ll +++ b/llvm/test/CodeGen/PowerPC/frameaddr.ll @@ -236,7 +236,7 @@ declare void @use(ptr) declare ptr @llvm.frameaddress(i32) #2 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } attributes #1 = { noreturn nounwind } attributes #2 = { nounwind readnone } -attributes #3 = { nounwind naked "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #3 = { nounwind naked "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/PowerPC/glob-comp-aa-crash.ll b/llvm/test/CodeGen/PowerPC/glob-comp-aa-crash.ll index 4c0c713..2726e8f 100644 --- a/llvm/test/CodeGen/PowerPC/glob-comp-aa-crash.ll +++ b/llvm/test/CodeGen/PowerPC/glob-comp-aa-crash.ll @@ -120,9 +120,9 @@ declare void @_ZNSt3__15mutex4lockEv(ptr) #0 ; Function Attrs: nounwind declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) #3 -attributes #0 = { optsize "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { noreturn optsize "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { optsize "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #1 = { nounwind optsize "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #2 = { noreturn optsize "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #3 = { nounwind } attributes #4 = { optsize } attributes #5 = { nounwind optsize } diff --git a/llvm/test/CodeGen/PowerPC/ifcvt-forked-bug-2016-08-08.ll b/llvm/test/CodeGen/PowerPC/ifcvt-forked-bug-2016-08-08.ll index 64c60bf..b00840a 100644 --- a/llvm/test/CodeGen/PowerPC/ifcvt-forked-bug-2016-08-08.ll +++ b/llvm/test/CodeGen/PowerPC/ifcvt-forked-bug-2016-08-08.ll @@ -34,5 +34,5 @@ declare ptr @_ZN11__sanitizer21internal_start_threadEPFvPvES0_(ptr, ptr) local_u declare hidden void @_ZN11__sanitizer16BackgroundThreadEPv(ptr nocapture readnone) #5 -attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "use-soft-float"="false" } attributes #7 = { nobuiltin nounwind } diff --git a/llvm/test/CodeGen/PowerPC/isel-rc-nox0.ll b/llvm/test/CodeGen/PowerPC/isel-rc-nox0.ll index d4daf24..e07fc29 100644 --- a/llvm/test/CodeGen/PowerPC/isel-rc-nox0.ll +++ b/llvm/test/CodeGen/PowerPC/isel-rc-nox0.ll @@ -42,5 +42,5 @@ func_80.exit2978.i: ; preds = %for.inc44.i2977.i ; Function Attrs: nounwind declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "ssp-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "ssp-buffer-size"="8" "use-soft-float"="false" } attributes #1 = { nounwind } diff --git a/llvm/test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll b/llvm/test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll index 2d471a0..f005899 100644 --- a/llvm/test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll +++ b/llvm/test/CodeGen/PowerPC/lxv-aligned-stack-slots.ll @@ -39,6 +39,6 @@ define void @aligned_slot() #0 { ; Function Attrs: argmemonly nounwind declare void @llvm.memcpy.p0.p0.i64(ptr nocapture writeonly, ptr nocapture readonly, i64, i1) #1 -attributes #0 = { nounwind "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "target-cpu"="pwr9" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+power9-vector,+vsx" "use-soft-float"="false" } attributes #1 = { argmemonly nounwind } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/PowerPC/mc-instrlat.ll b/llvm/test/CodeGen/PowerPC/mc-instrlat.ll index f807f4f..1ac5201 100644 --- a/llvm/test/CodeGen/PowerPC/mc-instrlat.ll +++ b/llvm/test/CodeGen/PowerPC/mc-instrlat.ll @@ -19,7 +19,7 @@ entry: declare void @bar(double) #1 -attributes #0 = { nounwind "no-infs-fp-math"="true" "no-nans-fp-math"="true" "target-cpu"="ppc64" "target-features"="+altivec,-bpermd,-crypto,-direct-move,-extdiv,-power8-vector,-vsx" "unsafe-fp-math"="true" "use-soft-float"="false" } -attributes #1 = { "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="ppc64" "target-features"="+altivec,-bpermd,-crypto,-direct-move,-extdiv,-power8-vector,-vsx" "unsafe-fp-math"="true" "use-soft-float"="false" } +attributes #0 = { nounwind "no-infs-fp-math"="true" "no-nans-fp-math"="true" "target-cpu"="ppc64" "target-features"="+altivec,-bpermd,-crypto,-direct-move,-extdiv,-power8-vector,-vsx" "use-soft-float"="false" } +attributes #1 = { "no-infs-fp-math"="true" "no-nans-fp-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="ppc64" "target-features"="+altivec,-bpermd,-crypto,-direct-move,-extdiv,-power8-vector,-vsx" "use-soft-float"="false" } attributes #2 = { nounwind } diff --git a/llvm/test/CodeGen/PowerPC/negctr.ll b/llvm/test/CodeGen/PowerPC/negctr.ll index 38664b0..e00a826 100644 --- a/llvm/test/CodeGen/PowerPC/negctr.ll +++ b/llvm/test/CodeGen/PowerPC/negctr.ll @@ -82,4 +82,4 @@ for.end: ; preds = %for.body, %entry ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/PowerPC/ppc-empty-fs.ll b/llvm/test/CodeGen/PowerPC/ppc-empty-fs.ll index 5c9bb12..66fa48e 100644 --- a/llvm/test/CodeGen/PowerPC/ppc-empty-fs.ll +++ b/llvm/test/CodeGen/PowerPC/ppc-empty-fs.ll @@ -21,7 +21,7 @@ entry: ; Function Attrs: nounwind declare void @llvm.memcpy.p0.p0.i64(ptr nocapture, ptr nocapture readonly, i64, i1) #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "target-features"="" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-realign-stack" "stack-protector-buffer-size"="8" "target-features"="" "use-soft-float"="false" } attributes #1 = { nounwind } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/PowerPC/ppc32-lshrti3.ll b/llvm/test/CodeGen/PowerPC/ppc32-lshrti3.ll index c9e183c..4499ea2 100644 --- a/llvm/test/CodeGen/PowerPC/ppc32-lshrti3.ll +++ b/llvm/test/CodeGen/PowerPC/ppc32-lshrti3.ll @@ -32,7 +32,7 @@ while.end: ; preds = %while.cond ret i32 undef } -attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind uwtable "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/PowerPC/pr17168.ll b/llvm/test/CodeGen/PowerPC/pr17168.ll index 828bc2b..160e3b1 100644 --- a/llvm/test/CodeGen/PowerPC/pr17168.ll +++ b/llvm/test/CodeGen/PowerPC/pr17168.ll @@ -51,7 +51,7 @@ for.cond1816.preheader.for.inc1898_crit_edge: ; preds = %for.cond1816.prehea ; Function Attrs: nounwind readnone declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #1 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #1 = { nounwind readnone } !llvm.dbg.cu = !{!7} diff --git a/llvm/test/CodeGen/PowerPC/pr17354.ll b/llvm/test/CodeGen/PowerPC/pr17354.ll index 38b98dff..9079371 100644 --- a/llvm/test/CodeGen/PowerPC/pr17354.ll +++ b/llvm/test/CodeGen/PowerPC/pr17354.ll @@ -35,4 +35,4 @@ entry: ret void } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/PowerPC/pr18663-2.ll b/llvm/test/CodeGen/PowerPC/pr18663-2.ll index 64d767a..97ad5b3 100644 --- a/llvm/test/CodeGen/PowerPC/pr18663-2.ll +++ b/llvm/test/CodeGen/PowerPC/pr18663-2.ll @@ -147,7 +147,7 @@ ehcleanup142: ; preds = %lpad19, %lpad.i.i.i resume { ptr, i32 } undef } -attributes #0 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { noreturn "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { inlinehint "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #1 = { noreturn "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #2 = { inlinehint "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/PowerPC/pr24546.ll b/llvm/test/CodeGen/PowerPC/pr24546.ll index 527139a..a84b2e8 100644 --- a/llvm/test/CodeGen/PowerPC/pr24546.ll +++ b/llvm/test/CodeGen/PowerPC/pr24546.ll @@ -47,8 +47,8 @@ declare double @pow(double, double) #0 ; Function Attrs: nounwind readnone declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #2 -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "use-soft-float"="false" } +attributes #1 = { "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "use-soft-float"="false" } attributes #2 = { nounwind readnone } attributes #3 = { nounwind } diff --git a/llvm/test/CodeGen/PowerPC/pr27350.ll b/llvm/test/CodeGen/PowerPC/pr27350.ll index 1a68f2c..568d7cd 100644 --- a/llvm/test/CodeGen/PowerPC/pr27350.ll +++ b/llvm/test/CodeGen/PowerPC/pr27350.ll @@ -18,7 +18,7 @@ entry: declare fastcc void @bar([2 x i64], [2 x i64]) unnamed_addr #1 align 2 attributes #0 = { argmemonly nounwind } -attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #1 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "use-soft-float"="false" } attributes #2 = { nounwind } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/PowerPC/pr28130.ll b/llvm/test/CodeGen/PowerPC/pr28130.ll index 135c6aa..21e4f3d 100644 --- a/llvm/test/CodeGen/PowerPC/pr28130.ll +++ b/llvm/test/CodeGen/PowerPC/pr28130.ll @@ -63,4 +63,4 @@ bb: ret void } -attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr8" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="pwr8" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+power8-vector,+vsx" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/PowerPC/reloc-align.ll b/llvm/test/CodeGen/PowerPC/reloc-align.ll index 1640e3d..d1524e5 100644 --- a/llvm/test/CodeGen/PowerPC/reloc-align.ll +++ b/llvm/test/CodeGen/PowerPC/reloc-align.ll @@ -30,4 +30,4 @@ entry: ret i32 %bf.cast } -attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir b/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir index 584f2a9..d0bcaef 100644 --- a/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir +++ b/llvm/test/CodeGen/PowerPC/rlwinm_rldicl_to_andi.mir @@ -60,7 +60,7 @@ ret i64 %cond } - attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { norecurse nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "use-soft-float"="false" } !llvm.module.flags = !{!0, !1} !llvm.ident = !{!2} diff --git a/llvm/test/CodeGen/PowerPC/setcr_bc.mir b/llvm/test/CodeGen/PowerPC/setcr_bc.mir index 76f9d5e..2823c0f 100644 --- a/llvm/test/CodeGen/PowerPC/setcr_bc.mir +++ b/llvm/test/CodeGen/PowerPC/setcr_bc.mir @@ -32,8 +32,8 @@ ret i32 %call2.i.sink } - attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "unsafe-fp-math"="false" "use-soft-float"="false" } - attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "use-soft-float"="false" } + attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "use-soft-float"="false" } ... --- diff --git a/llvm/test/CodeGen/PowerPC/setcr_bc2.mir b/llvm/test/CodeGen/PowerPC/setcr_bc2.mir index 433ea63..ca88ec7 100644 --- a/llvm/test/CodeGen/PowerPC/setcr_bc2.mir +++ b/llvm/test/CodeGen/PowerPC/setcr_bc2.mir @@ -32,8 +32,8 @@ ret i32 %call2.i.sink } - attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "unsafe-fp-math"="false" "use-soft-float"="false" } - attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "use-soft-float"="false" } + attributes #1 = { "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "use-soft-float"="false" } ... --- diff --git a/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir b/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir index ee16a8c..2ffca9c 100644 --- a/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir +++ b/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-1.mir @@ -155,7 +155,7 @@ ; Function Attrs: noduplicate nounwind declare i1 @llvm.loop.decrement.i64(i64) #1 - attributes #0 = { nofree norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector,-spe" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { nofree norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector,-spe" "use-soft-float"="false" } attributes #1 = { noduplicate nounwind } !llvm.module.flags = !{!0} diff --git a/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-regpressure-high.mir b/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-regpressure-high.mir index 4069fec..261ed55 100644 --- a/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-regpressure-high.mir +++ b/llvm/test/CodeGen/PowerPC/sink-down-more-instructions-regpressure-high.mir @@ -239,7 +239,7 @@ ; Function Attrs: noduplicate nounwind declare i1 @llvm.loop.decrement.i64(i64) #1 - attributes #0 = { nofree norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector,-spe" "unsafe-fp-math"="false" "use-soft-float"="false" } + attributes #0 = { nofree norecurse nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector,-spe" "use-soft-float"="false" } attributes #1 = { noduplicate nounwind } !llvm.module.flags = !{!0} diff --git a/llvm/test/CodeGen/PowerPC/sjlj.ll b/llvm/test/CodeGen/PowerPC/sjlj.ll index 88a6cfd..92b0c5c 100644 --- a/llvm/test/CodeGen/PowerPC/sjlj.ll +++ b/llvm/test/CodeGen/PowerPC/sjlj.ll @@ -171,7 +171,7 @@ declare ptr @llvm.stacksave() #3 declare i32 @llvm.eh.sjlj.setjmp(ptr) #3 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } attributes #1 = { noreturn nounwind } attributes #2 = { nounwind readnone } attributes #3 = { nounwind } diff --git a/llvm/test/CodeGen/PowerPC/stwu-sched.ll b/llvm/test/CodeGen/PowerPC/stwu-sched.ll index 4cf07c3..29a5efc 100644 --- a/llvm/test/CodeGen/PowerPC/stwu-sched.ll +++ b/llvm/test/CodeGen/PowerPC/stwu-sched.ll @@ -58,7 +58,7 @@ define void @initCombList(ptr nocapture, i32 signext) local_unnamed_addr #0 { ret void } -attributes #0 = { norecurse nounwind writeonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { norecurse nounwind writeonly "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "use-soft-float"="false" } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/PowerPC/toc-load-sched-bug.ll b/llvm/test/CodeGen/PowerPC/toc-load-sched-bug.ll index 7418767..37fe763 100644 --- a/llvm/test/CodeGen/PowerPC/toc-load-sched-bug.ll +++ b/llvm/test/CodeGen/PowerPC/toc-load-sched-bug.ll @@ -475,13 +475,13 @@ declare void @_ZNSs4swapERSs(ptr, ptr dereferenceable(8)) #1 ; Function Attrs: nounwind declare void @llvm.memset.p0.i64(ptr nocapture, i8, i64, i1) #3 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #2 = { inlinehint nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #1 = { "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #2 = { inlinehint nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #3 = { nounwind } -attributes #4 = { noreturn nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #5 = { nounwind readonly "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } -attributes #6 = { nobuiltin nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #4 = { noreturn nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #5 = { nounwind readonly "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } +attributes #6 = { nobuiltin nounwind "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "stack-protector-buffer-size"="8" "use-soft-float"="false" } attributes #7 = { noreturn nounwind } !llvm.ident = !{!0} diff --git a/llvm/test/CodeGen/PowerPC/unal4-std.ll b/llvm/test/CodeGen/PowerPC/unal4-std.ll index 04fd525..4a5fb39 100644 --- a/llvm/test/CodeGen/PowerPC/unal4-std.ll +++ b/llvm/test/CodeGen/PowerPC/unal4-std.ll @@ -34,4 +34,4 @@ if.end210: ; preds = %entry } -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="non-leaf" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/PowerPC/uwtables.ll b/llvm/test/CodeGen/PowerPC/uwtables.ll index f9f35d9..3c3a108 100644 --- a/llvm/test/CodeGen/PowerPC/uwtables.ll +++ b/llvm/test/CodeGen/PowerPC/uwtables.ll @@ -46,5 +46,5 @@ declare i32 @__gxx_personality_v0(...) declare void @__cxa_call_unexpected(ptr) local_unnamed_addr -attributes #0 = { noreturn nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { noreturn nounwind "correctly-rounded-divide-sqrt-fp-math"="false" "disable-tail-calls"="false" "less-precise-fpmad"="false" "frame-pointer"="none" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="false" "stack-protector-buffer-size"="8" "target-cpu"="ppc64le" "target-features"="+altivec,+bpermd,+crypto,+direct-move,+extdiv,+htm,+power8-vector,+vsx,-power9-vector" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/PowerPC/zero-not-run.ll b/llvm/test/CodeGen/PowerPC/zero-not-run.ll index 6d43191..3c26554 100644 --- a/llvm/test/CodeGen/PowerPC/zero-not-run.ll +++ b/llvm/test/CodeGen/PowerPC/zero-not-run.ll @@ -24,4 +24,4 @@ for.end731: ; preds = %entry ; Function Attrs: nounwind declare i64 @safe_mod_func_uint64_t_u_u(i64, i64) #0 -attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } +attributes #0 = { nounwind "less-precise-fpmad"="false" "frame-pointer"="all" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "use-soft-float"="false" } diff --git a/llvm/test/CodeGen/RISCV/rv32p.ll b/llvm/test/CodeGen/RISCV/rv32p.ll new file mode 100644 index 0000000..4eee880a --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rv32p.ll @@ -0,0 +1,709 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -mattr=+experimental-p -verify-machineinstrs < %s \ +; RUN: | FileCheck %s + +declare i32 @llvm.ctlz.i32(i32, i1) + +define i32 @ctlz_i32(i32 %a) nounwind { +; CHECK-LABEL: ctlz_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: clz a0, a0 +; CHECK-NEXT: ret + %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false) + ret i32 %1 +} + +declare i64 @llvm.ctlz.i64(i64, i1) + +define i64 @ctlz_i64(i64 %a) nounwind { +; CHECK-LABEL: ctlz_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: bnez a1, .LBB1_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: clz a0, a0 +; CHECK-NEXT: addi a0, a0, 32 +; CHECK-NEXT: li a1, 0 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB1_2: +; CHECK-NEXT: clz a0, a1 +; CHECK-NEXT: li a1, 0 +; CHECK-NEXT: ret + %1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false) + ret i64 %1 +} + +declare i32 @llvm.cttz.i32(i32, i1) + +define i32 @cttz_i32(i32 %a) nounwind { +; CHECK-LABEL: cttz_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: beqz a0, .LBB2_2 +; CHECK-NEXT: # %bb.1: # %cond.false +; CHECK-NEXT: addi a1, a0, -1 +; CHECK-NEXT: not a0, a0 +; CHECK-NEXT: and a0, a0, a1 +; CHECK-NEXT: clz a0, a0 +; CHECK-NEXT: li a1, 32 +; CHECK-NEXT: sub a0, a1, a0 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB2_2: +; CHECK-NEXT: li a0, 32 +; CHECK-NEXT: ret + %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false) + ret i32 %1 +} + +declare i64 @llvm.cttz.i64(i64, i1) + +define i64 @cttz_i64(i64 %a) nounwind { +; CHECK-LABEL: cttz_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: or a2, a0, a1 +; CHECK-NEXT: beqz a2, .LBB3_3 +; CHECK-NEXT: # %bb.1: # %cond.false +; CHECK-NEXT: bnez a0, .LBB3_4 +; CHECK-NEXT: # %bb.2: # %cond.false +; CHECK-NEXT: addi a0, a1, -1 +; CHECK-NEXT: not a1, a1 +; CHECK-NEXT: and a0, a1, a0 +; CHECK-NEXT: clz a0, a0 +; CHECK-NEXT: li a1, 64 +; CHECK-NEXT: j .LBB3_5 +; CHECK-NEXT: .LBB3_3: +; CHECK-NEXT: li a1, 0 +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB3_4: +; CHECK-NEXT: addi a1, a0, -1 +; CHECK-NEXT: not a0, a0 +; CHECK-NEXT: and a0, a0, a1 +; CHECK-NEXT: clz a0, a0 +; CHECK-NEXT: li a1, 32 +; CHECK-NEXT: .LBB3_5: # %cond.false +; CHECK-NEXT: sub a0, a1, a0 +; CHECK-NEXT: li a1, 0 +; CHECK-NEXT: ret + %1 = call i64 @llvm.cttz.i64(i64 %a, i1 false) + ret i64 %1 +} + +define i32 @sextb_i32(i32 %a) nounwind { +; CHECK-LABEL: sextb_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: sext.b a0, a0 +; CHECK-NEXT: ret + %shl = shl i32 %a, 24 + %shr = ashr exact i32 %shl, 24 + ret i32 %shr +} + +define i64 @sextb_i64(i64 %a) nounwind { +; CHECK-LABEL: sextb_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: sext.b a0, a0 +; CHECK-NEXT: srai a1, a0, 31 +; CHECK-NEXT: ret + %shl = shl i64 %a, 56 + %shr = ashr exact i64 %shl, 56 + ret i64 %shr +} + +define i32 @sexth_i32(i32 %a) nounwind { +; CHECK-LABEL: sexth_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: sext.h a0, a0 +; CHECK-NEXT: ret + %shl = shl i32 %a, 16 + %shr = ashr exact i32 %shl, 16 + ret i32 %shr +} + +define i64 @sexth_i64(i64 %a) nounwind { +; CHECK-LABEL: sexth_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: sext.h a0, a0 +; CHECK-NEXT: srai a1, a0, 31 +; CHECK-NEXT: ret + %shl = shl i64 %a, 48 + %shr = ashr exact i64 %shl, 48 + ret i64 %shr +} + +define i32 @min_i32(i32 %a, i32 %b) nounwind { +; CHECK-LABEL: min_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: min a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp slt i32 %a, %b + %cond = select i1 %cmp, i32 %a, i32 %b + ret i32 %cond +} + +; As we are not matching directly i64 code patterns on RV32 some i64 patterns +; don't have yet any matching bit manipulation instructions on RV32. +; This test is presented here in case future expansions of the Bitmanip +; extensions introduce instructions suitable for this pattern. + +define i64 @min_i64(i64 %a, i64 %b) nounwind { +; CHECK-LABEL: min_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: beq a1, a3, .LBB9_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: slt a4, a1, a3 +; CHECK-NEXT: beqz a4, .LBB9_3 +; CHECK-NEXT: j .LBB9_4 +; CHECK-NEXT: .LBB9_2: +; CHECK-NEXT: sltu a4, a0, a2 +; CHECK-NEXT: bnez a4, .LBB9_4 +; CHECK-NEXT: .LBB9_3: +; CHECK-NEXT: mv a0, a2 +; CHECK-NEXT: mv a1, a3 +; CHECK-NEXT: .LBB9_4: +; CHECK-NEXT: ret + %cmp = icmp slt i64 %a, %b + %cond = select i1 %cmp, i64 %a, i64 %b + ret i64 %cond +} + +define i32 @max_i32(i32 %a, i32 %b) nounwind { +; CHECK-LABEL: max_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: max a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp sgt i32 %a, %b + %cond = select i1 %cmp, i32 %a, i32 %b + ret i32 %cond +} + +; As we are not matching directly i64 code patterns on RV32 some i64 patterns +; don't have yet any matching bit manipulation instructions on RV32. +; This test is presented here in case future expansions of the Bitmanip +; extensions introduce instructions suitable for this pattern. + +define i64 @max_i64(i64 %a, i64 %b) nounwind { +; CHECK-LABEL: max_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: beq a1, a3, .LBB11_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: slt a4, a3, a1 +; CHECK-NEXT: beqz a4, .LBB11_3 +; CHECK-NEXT: j .LBB11_4 +; CHECK-NEXT: .LBB11_2: +; CHECK-NEXT: sltu a4, a2, a0 +; CHECK-NEXT: bnez a4, .LBB11_4 +; CHECK-NEXT: .LBB11_3: +; CHECK-NEXT: mv a0, a2 +; CHECK-NEXT: mv a1, a3 +; CHECK-NEXT: .LBB11_4: +; CHECK-NEXT: ret + %cmp = icmp sgt i64 %a, %b + %cond = select i1 %cmp, i64 %a, i64 %b + ret i64 %cond +} + +define i32 @minu_i32(i32 %a, i32 %b) nounwind { +; CHECK-LABEL: minu_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: minu a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp ult i32 %a, %b + %cond = select i1 %cmp, i32 %a, i32 %b + ret i32 %cond +} + +; As we are not matching directly i64 code patterns on RV32 some i64 patterns +; don't have yet any matching bit manipulation instructions on RV32. +; This test is presented here in case future expansions of the Bitmanip +; extensions introduce instructions suitable for this pattern. + +define i64 @minu_i64(i64 %a, i64 %b) nounwind { +; CHECK-LABEL: minu_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: beq a1, a3, .LBB13_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: sltu a4, a1, a3 +; CHECK-NEXT: beqz a4, .LBB13_3 +; CHECK-NEXT: j .LBB13_4 +; CHECK-NEXT: .LBB13_2: +; CHECK-NEXT: sltu a4, a0, a2 +; CHECK-NEXT: bnez a4, .LBB13_4 +; CHECK-NEXT: .LBB13_3: +; CHECK-NEXT: mv a0, a2 +; CHECK-NEXT: mv a1, a3 +; CHECK-NEXT: .LBB13_4: +; CHECK-NEXT: ret + %cmp = icmp ult i64 %a, %b + %cond = select i1 %cmp, i64 %a, i64 %b + ret i64 %cond +} + +define i32 @maxu_i32(i32 %a, i32 %b) nounwind { +; CHECK-LABEL: maxu_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: maxu a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp ugt i32 %a, %b + %cond = select i1 %cmp, i32 %a, i32 %b + ret i32 %cond +} + +; As we are not matching directly i64 code patterns on RV32 some i64 patterns +; don't have yet any matching bit manipulation instructions on RV32. +; This test is presented here in case future expansions of the Bitmanip +; extensions introduce instructions suitable for this pattern. + +define i64 @maxu_i64(i64 %a, i64 %b) nounwind { +; CHECK-LABEL: maxu_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: beq a1, a3, .LBB15_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: sltu a4, a3, a1 +; CHECK-NEXT: beqz a4, .LBB15_3 +; CHECK-NEXT: j .LBB15_4 +; CHECK-NEXT: .LBB15_2: +; CHECK-NEXT: sltu a4, a2, a0 +; CHECK-NEXT: bnez a4, .LBB15_4 +; CHECK-NEXT: .LBB15_3: +; CHECK-NEXT: mv a0, a2 +; CHECK-NEXT: mv a1, a3 +; CHECK-NEXT: .LBB15_4: +; CHECK-NEXT: ret + %cmp = icmp ugt i64 %a, %b + %cond = select i1 %cmp, i64 %a, i64 %b + ret i64 %cond +} + +declare i32 @llvm.abs.i32(i32, i1 immarg) + +define i32 @abs_i32(i32 %x) { +; CHECK-LABEL: abs_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: abs a0, a0 +; CHECK-NEXT: ret + %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) + ret i32 %abs +} + +declare i64 @llvm.abs.i64(i64, i1 immarg) + +define i64 @abs_i64(i64 %x) { +; CHECK-LABEL: abs_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: bgez a1, .LBB17_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: snez a2, a0 +; CHECK-NEXT: neg a0, a0 +; CHECK-NEXT: neg a1, a1 +; CHECK-NEXT: sub a1, a1, a2 +; CHECK-NEXT: .LBB17_2: +; CHECK-NEXT: ret + %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) + ret i64 %abs +} + +define i32 @zexth_i32(i32 %a) nounwind { +; CHECK-LABEL: zexth_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a0, a0, 16 +; CHECK-NEXT: srli a0, a0, 16 +; CHECK-NEXT: ret + %and = and i32 %a, 65535 + ret i32 %and +} + +define i64 @zexth_i64(i64 %a) nounwind { +; CHECK-LABEL: zexth_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a0, a0, 16 +; CHECK-NEXT: srli a0, a0, 16 +; CHECK-NEXT: li a1, 0 +; CHECK-NEXT: ret + %and = and i64 %a, 65535 + ret i64 %and +} + +declare i32 @llvm.bswap.i32(i32) + +define i32 @bswap_i32(i32 %a) nounwind { +; CHECK-LABEL: bswap_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: rev8 a0, a0 +; CHECK-NEXT: ret + %1 = tail call i32 @llvm.bswap.i32(i32 %a) + ret i32 %1 +} + +declare i64 @llvm.bswap.i64(i64) + +define i64 @bswap_i64(i64 %a) { +; CHECK-LABEL: bswap_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: rev8 a2, a1 +; CHECK-NEXT: rev8 a1, a0 +; CHECK-NEXT: mv a0, a2 +; CHECK-NEXT: ret + %1 = call i64 @llvm.bswap.i64(i64 %a) + ret i64 %1 +} + +define i32 @srai_slli(i16 signext %0) { +; CHECK-LABEL: srai_slli: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a0, a0, 25 +; CHECK-NEXT: srai a0, a0, 31 +; CHECK-NEXT: ret + %2 = shl i16 %0, 9 + %sext = ashr i16 %2, 15 + %3 = sext i16 %sext to i32 + ret i32 %3 +} + +define i32 @srai_slli2(i16 signext %0) { +; CHECK-LABEL: srai_slli2: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a0, a0, 25 +; CHECK-NEXT: srai a0, a0, 30 +; CHECK-NEXT: ret + %2 = shl i16 %0, 9 + %sext = ashr i16 %2, 14 + %3 = sext i16 %sext to i32 + ret i32 %3 +} +define i8 @sub_if_uge_i8(i8 %x, i8 %y) { +; CHECK-LABEL: sub_if_uge_i8: +; CHECK: # %bb.0: +; CHECK-NEXT: zext.b a2, a0 +; CHECK-NEXT: sub a0, a0, a1 +; CHECK-NEXT: zext.b a0, a0 +; CHECK-NEXT: minu a0, a2, a0 +; CHECK-NEXT: ret + %cmp = icmp ult i8 %x, %y + %select = select i1 %cmp, i8 0, i8 %y + %sub = sub nuw i8 %x, %select + ret i8 %sub +} + +define i16 @sub_if_uge_i16(i16 %x, i16 %y) { +; CHECK-LABEL: sub_if_uge_i16: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a2, 16 +; CHECK-NEXT: sub a1, a0, a1 +; CHECK-NEXT: addi a2, a2, -1 +; CHECK-NEXT: and a0, a0, a2 +; CHECK-NEXT: and a1, a1, a2 +; CHECK-NEXT: minu a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp ult i16 %x, %y + %select = select i1 %cmp, i16 0, i16 %y + %sub = sub nuw i16 %x, %select + ret i16 %sub +} + +define i32 @sub_if_uge_i32(i32 %x, i32 %y) { +; CHECK-LABEL: sub_if_uge_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: sub a1, a0, a1 +; CHECK-NEXT: minu a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp ult i32 %x, %y + %select = select i1 %cmp, i32 0, i32 %y + %sub = sub nuw i32 %x, %select + ret i32 %sub +} + +define i64 @sub_if_uge_i64(i64 %x, i64 %y) { +; CHECK-LABEL: sub_if_uge_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: beq a1, a3, .LBB27_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: sltu a4, a1, a3 +; CHECK-NEXT: j .LBB27_3 +; CHECK-NEXT: .LBB27_2: +; CHECK-NEXT: sltu a4, a0, a2 +; CHECK-NEXT: .LBB27_3: +; CHECK-NEXT: addi a4, a4, -1 +; CHECK-NEXT: and a3, a4, a3 +; CHECK-NEXT: and a2, a4, a2 +; CHECK-NEXT: sltu a4, a0, a2 +; CHECK-NEXT: sub a1, a1, a3 +; CHECK-NEXT: sub a1, a1, a4 +; CHECK-NEXT: sub a0, a0, a2 +; CHECK-NEXT: ret + %cmp = icmp ult i64 %x, %y + %select = select i1 %cmp, i64 0, i64 %y + %sub = sub nuw i64 %x, %select + ret i64 %sub +} + +define i128 @sub_if_uge_i128(i128 %x, i128 %y) { +; CHECK-LABEL: sub_if_uge_i128: +; CHECK: # %bb.0: +; CHECK-NEXT: lw a3, 4(a1) +; CHECK-NEXT: lw a4, 8(a1) +; CHECK-NEXT: lw a5, 12(a1) +; CHECK-NEXT: lw a6, 4(a2) +; CHECK-NEXT: lw t0, 12(a2) +; CHECK-NEXT: lw a7, 8(a2) +; CHECK-NEXT: beq a5, t0, .LBB28_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: sltu t1, a5, t0 +; CHECK-NEXT: j .LBB28_3 +; CHECK-NEXT: .LBB28_2: +; CHECK-NEXT: sltu t1, a4, a7 +; CHECK-NEXT: .LBB28_3: +; CHECK-NEXT: lw a1, 0(a1) +; CHECK-NEXT: lw a2, 0(a2) +; CHECK-NEXT: beq a3, a6, .LBB28_5 +; CHECK-NEXT: # %bb.4: +; CHECK-NEXT: sltu t2, a3, a6 +; CHECK-NEXT: j .LBB28_6 +; CHECK-NEXT: .LBB28_5: +; CHECK-NEXT: sltu t2, a1, a2 +; CHECK-NEXT: .LBB28_6: +; CHECK-NEXT: xor t3, a5, t0 +; CHECK-NEXT: xor t4, a4, a7 +; CHECK-NEXT: or t3, t4, t3 +; CHECK-NEXT: beqz t3, .LBB28_8 +; CHECK-NEXT: # %bb.7: +; CHECK-NEXT: mv t2, t1 +; CHECK-NEXT: .LBB28_8: +; CHECK-NEXT: addi t3, t2, -1 +; CHECK-NEXT: and t2, t3, t0 +; CHECK-NEXT: and t0, t3, a2 +; CHECK-NEXT: and t1, t3, a6 +; CHECK-NEXT: sltu a2, a1, t0 +; CHECK-NEXT: and a7, t3, a7 +; CHECK-NEXT: mv a6, a2 +; CHECK-NEXT: beq a3, t1, .LBB28_10 +; CHECK-NEXT: # %bb.9: +; CHECK-NEXT: sltu a6, a3, t1 +; CHECK-NEXT: .LBB28_10: +; CHECK-NEXT: sub t3, a4, a7 +; CHECK-NEXT: sltu a4, a4, a7 +; CHECK-NEXT: sub a5, a5, t2 +; CHECK-NEXT: sub a3, a3, t1 +; CHECK-NEXT: sub a1, a1, t0 +; CHECK-NEXT: sltu a7, t3, a6 +; CHECK-NEXT: sub a5, a5, a4 +; CHECK-NEXT: sub a4, t3, a6 +; CHECK-NEXT: sub a3, a3, a2 +; CHECK-NEXT: sub a2, a5, a7 +; CHECK-NEXT: sw a1, 0(a0) +; CHECK-NEXT: sw a3, 4(a0) +; CHECK-NEXT: sw a4, 8(a0) +; CHECK-NEXT: sw a2, 12(a0) +; CHECK-NEXT: ret + %cmp = icmp ult i128 %x, %y + %select = select i1 %cmp, i128 0, i128 %y + %sub = sub nuw i128 %x, %select + ret i128 %sub +} + +define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) { +; CHECK-LABEL: sub_if_uge_multiuse_select_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: sltu a2, a0, a1 +; CHECK-NEXT: addi a2, a2, -1 +; CHECK-NEXT: and a1, a2, a1 +; CHECK-NEXT: sub a0, a0, a1 +; CHECK-NEXT: sll a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp ult i32 %x, %y + %select = select i1 %cmp, i32 0, i32 %y + %sub = sub nuw i32 %x, %select + %shl = shl i32 %sub, %select + ret i32 %shl +} + +define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) { +; CHECK-LABEL: sub_if_uge_multiuse_cmp_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: sub a2, a0, a1 +; CHECK-NEXT: minu a2, a0, a2 +; CHECK-NEXT: bltu a0, a1, .LBB30_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: li a0, 4 +; CHECK-NEXT: sll a0, a2, a0 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB30_2: +; CHECK-NEXT: li a0, 2 +; CHECK-NEXT: sll a0, a2, a0 +; CHECK-NEXT: ret + %cmp = icmp ult i32 %x, %y + %select = select i1 %cmp, i32 0, i32 %y + %sub = sub nuw i32 %x, %select + %select2 = select i1 %cmp, i32 2, i32 4 + %shl = shl i32 %sub, %select2 + ret i32 %shl +} + +define i32 @sub_if_uge_multiuse_cmp_store_i32(i32 %x, i32 %y, ptr %z) { +; CHECK-LABEL: sub_if_uge_multiuse_cmp_store_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: sltu a3, a0, a1 +; CHECK-NEXT: sub a1, a0, a1 +; CHECK-NEXT: xori a3, a3, 1 +; CHECK-NEXT: minu a0, a0, a1 +; CHECK-NEXT: sw a3, 0(a2) +; CHECK-NEXT: ret + %cmp = icmp uge i32 %x, %y + %conv = zext i1 %cmp to i32 + store i32 %conv, ptr %z, align 4 + %select = select i1 %cmp, i32 %y, i32 0 + %sub = sub nuw i32 %x, %select + ret i32 %sub +} + +define i8 @sub_if_uge_C_i8(i8 zeroext %x) { +; CHECK-LABEL: sub_if_uge_C_i8: +; CHECK: # %bb.0: +; CHECK-NEXT: addi a1, a0, -13 +; CHECK-NEXT: zext.b a1, a1 +; CHECK-NEXT: minu a0, a1, a0 +; CHECK-NEXT: ret + %cmp = icmp ugt i8 %x, 12 + %sub = add i8 %x, -13 + %conv4 = select i1 %cmp, i8 %sub, i8 %x + ret i8 %conv4 +} + +define i16 @sub_if_uge_C_i16(i16 zeroext %x) { +; CHECK-LABEL: sub_if_uge_C_i16: +; CHECK: # %bb.0: +; CHECK-NEXT: addi a1, a0, -251 +; CHECK-NEXT: slli a1, a1, 16 +; CHECK-NEXT: srli a1, a1, 16 +; CHECK-NEXT: minu a0, a1, a0 +; CHECK-NEXT: ret + %cmp = icmp ugt i16 %x, 250 + %sub = add i16 %x, -251 + %conv4 = select i1 %cmp, i16 %sub, i16 %x + ret i16 %conv4 +} + +define i32 @sub_if_uge_C_i32(i32 signext %x) { +; CHECK-LABEL: sub_if_uge_C_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a1, 1048560 +; CHECK-NEXT: addi a1, a1, 15 +; CHECK-NEXT: add a1, a0, a1 +; CHECK-NEXT: minu a0, a1, a0 +; CHECK-NEXT: ret + %cmp = icmp ugt i32 %x, 65520 + %sub = add i32 %x, -65521 + %cond = select i1 %cmp, i32 %sub, i32 %x + ret i32 %cond +} + +define i64 @sub_if_uge_C_i64(i64 %x) { +; CHECK-LABEL: sub_if_uge_C_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: li a2, 1 +; CHECK-NEXT: beq a1, a2, .LBB35_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: sltiu a2, a1, 2 +; CHECK-NEXT: xori a2, a2, 1 +; CHECK-NEXT: j .LBB35_3 +; CHECK-NEXT: .LBB35_2: +; CHECK-NEXT: lui a2, 172127 +; CHECK-NEXT: addi a2, a2, 511 +; CHECK-NEXT: sltu a2, a2, a0 +; CHECK-NEXT: .LBB35_3: +; CHECK-NEXT: neg a2, a2 +; CHECK-NEXT: andi a3, a2, -2 +; CHECK-NEXT: add a1, a1, a3 +; CHECK-NEXT: lui a3, 876449 +; CHECK-NEXT: addi a3, a3, -512 +; CHECK-NEXT: and a2, a2, a3 +; CHECK-NEXT: add a2, a0, a2 +; CHECK-NEXT: sltu a0, a2, a0 +; CHECK-NEXT: add a1, a1, a0 +; CHECK-NEXT: mv a0, a2 +; CHECK-NEXT: ret + %cmp = icmp ugt i64 %x, 4999999999 + %sub = add i64 %x, -5000000000 + %cond = select i1 %cmp, i64 %sub, i64 %x + ret i64 %cond +} + +define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) { +; CHECK-LABEL: sub_if_uge_C_multiuse_cmp_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a2, 16 +; CHECK-NEXT: lui a3, 1048560 +; CHECK-NEXT: addi a2, a2, -16 +; CHECK-NEXT: addi a3, a3, 15 +; CHECK-NEXT: sltu a2, a2, a0 +; CHECK-NEXT: add a3, a0, a3 +; CHECK-NEXT: minu a0, a3, a0 +; CHECK-NEXT: sw a2, 0(a1) +; CHECK-NEXT: ret + %cmp = icmp ugt i32 %x, 65520 + %conv = zext i1 %cmp to i32 + store i32 %conv, ptr %z, align 4 + %sub = add i32 %x, -65521 + %cond = select i1 %cmp, i32 %sub, i32 %x + ret i32 %cond +} + +define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) { +; CHECK-LABEL: sub_if_uge_C_multiuse_sub_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a2, 1048560 +; CHECK-NEXT: addi a2, a2, 15 +; CHECK-NEXT: add a2, a0, a2 +; CHECK-NEXT: minu a0, a2, a0 +; CHECK-NEXT: sw a2, 0(a1) +; CHECK-NEXT: ret + %sub = add i32 %x, -65521 + store i32 %sub, ptr %z, align 4 + %cmp = icmp ugt i32 %x, 65520 + %cond = select i1 %cmp, i32 %sub, i32 %x + ret i32 %cond +} + +define i32 @sub_if_uge_C_swapped_i32(i32 %x) { +; CHECK-LABEL: sub_if_uge_C_swapped_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a1, 1048560 +; CHECK-NEXT: addi a1, a1, 15 +; CHECK-NEXT: add a1, a0, a1 +; CHECK-NEXT: minu a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp ult i32 %x, 65521 + %sub = add i32 %x, -65521 + %cond = select i1 %cmp, i32 %x, i32 %sub + ret i32 %cond +} + +define i7 @sub_if_uge_C_nsw_i7(i7 %a) { +; CHECK-LABEL: sub_if_uge_C_nsw_i7: +; CHECK: # %bb.0: +; CHECK-NEXT: ori a0, a0, 51 +; CHECK-NEXT: andi a1, a0, 127 +; CHECK-NEXT: addi a0, a0, 17 +; CHECK-NEXT: andi a0, a0, 92 +; CHECK-NEXT: minu a0, a0, a1 +; CHECK-NEXT: ret + %x = or i7 %a, 51 + %c = icmp ugt i7 %x, -18 + %add = add nsw i7 %x, 17 + %s = select i1 %c, i7 %add, i7 %x + ret i7 %s +} + +define i7 @sub_if_uge_C_swapped_nsw_i7(i7 %a) { +; CHECK-LABEL: sub_if_uge_C_swapped_nsw_i7: +; CHECK: # %bb.0: +; CHECK-NEXT: ori a0, a0, 51 +; CHECK-NEXT: andi a1, a0, 127 +; CHECK-NEXT: addi a0, a0, 17 +; CHECK-NEXT: andi a0, a0, 92 +; CHECK-NEXT: minu a0, a1, a0 +; CHECK-NEXT: ret + %x = or i7 %a, 51 + %c = icmp ult i7 %x, -17 + %add = add nsw i7 %x, 17 + %s = select i1 %c, i7 %x, i7 %add + ret i7 %s +} diff --git a/llvm/test/CodeGen/RISCV/rv64p.ll b/llvm/test/CodeGen/RISCV/rv64p.ll new file mode 100644 index 0000000..cb07f94 --- /dev/null +++ b/llvm/test/CodeGen/RISCV/rv64p.ll @@ -0,0 +1,677 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv64 -mattr=+experimental-p -verify-machineinstrs < %s \ +; RUN: | FileCheck %s + +declare i32 @llvm.ctlz.i32(i32, i1) + +define signext i32 @ctlz_i32(i32 signext %a) nounwind { +; CHECK-LABEL: ctlz_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: clzw a0, a0 +; CHECK-NEXT: ret + %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false) + ret i32 %1 +} + +define signext i32 @log2_i32(i32 signext %a) nounwind { +; CHECK-LABEL: log2_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: clzw a0, a0 +; CHECK-NEXT: li a1, 31 +; CHECK-NEXT: sub a0, a1, a0 +; CHECK-NEXT: ret + %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 false) + %2 = sub i32 31, %1 + ret i32 %2 +} + +define signext i32 @log2_ceil_i32(i32 signext %a) nounwind { +; CHECK-LABEL: log2_ceil_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: clzw a0, a0 +; CHECK-NEXT: li a1, 32 +; CHECK-NEXT: sub a0, a1, a0 +; CHECK-NEXT: ret + %1 = sub i32 %a, 1 + %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) + %3 = sub i32 32, %2 + ret i32 %3 +} + +define signext i32 @findLastSet_i32(i32 signext %a) nounwind { +; CHECK-LABEL: findLastSet_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: clzw a1, a0 +; CHECK-NEXT: snez a0, a0 +; CHECK-NEXT: xori a1, a1, 31 +; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: or a0, a0, a1 +; CHECK-NEXT: ret + %1 = call i32 @llvm.ctlz.i32(i32 %a, i1 true) + %2 = xor i32 31, %1 + %3 = icmp eq i32 %a, 0 + %4 = select i1 %3, i32 -1, i32 %2 + ret i32 %4 +} + +define i32 @ctlz_lshr_i32(i32 signext %a) { +; CHECK-LABEL: ctlz_lshr_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: srliw a0, a0, 1 +; CHECK-NEXT: clzw a0, a0 +; CHECK-NEXT: ret + %1 = lshr i32 %a, 1 + %2 = call i32 @llvm.ctlz.i32(i32 %1, i1 false) + ret i32 %2 +} + +declare i64 @llvm.ctlz.i64(i64, i1) + +define i64 @ctlz_i64(i64 %a) nounwind { +; CHECK-LABEL: ctlz_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: clz a0, a0 +; CHECK-NEXT: ret + %1 = call i64 @llvm.ctlz.i64(i64 %a, i1 false) + ret i64 %1 +} + +declare i32 @llvm.cttz.i32(i32, i1) + +define signext i32 @cttz_i32(i32 signext %a) nounwind { +; CHECK-LABEL: cttz_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: beqz a0, .LBB6_2 +; CHECK-NEXT: # %bb.1: # %cond.false +; CHECK-NEXT: addi a1, a0, -1 +; CHECK-NEXT: not a0, a0 +; CHECK-NEXT: and a0, a0, a1 +; CHECK-NEXT: clzw a0, a0 +; CHECK-NEXT: li a1, 32 +; CHECK-NEXT: sub a0, a1, a0 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB6_2: +; CHECK-NEXT: li a0, 32 +; CHECK-NEXT: ret + %1 = call i32 @llvm.cttz.i32(i32 %a, i1 false) + ret i32 %1 +} + +define signext i32 @cttz_zero_undef_i32(i32 signext %a) nounwind { +; CHECK-LABEL: cttz_zero_undef_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: addi a1, a0, -1 +; CHECK-NEXT: not a0, a0 +; CHECK-NEXT: and a0, a0, a1 +; CHECK-NEXT: clzw a0, a0 +; CHECK-NEXT: li a1, 32 +; CHECK-NEXT: sub a0, a1, a0 +; CHECK-NEXT: ret + %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true) + ret i32 %1 +} + +define signext i32 @findFirstSet_i32(i32 signext %a) nounwind { +; CHECK-LABEL: findFirstSet_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: addi a1, a0, -1 +; CHECK-NEXT: not a2, a0 +; CHECK-NEXT: and a1, a2, a1 +; CHECK-NEXT: li a2, 32 +; CHECK-NEXT: snez a0, a0 +; CHECK-NEXT: clzw a1, a1 +; CHECK-NEXT: sub a2, a2, a1 +; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: or a0, a0, a2 +; CHECK-NEXT: ret + %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true) + %2 = icmp eq i32 %a, 0 + %3 = select i1 %2, i32 -1, i32 %1 + ret i32 %3 +} + +define signext i32 @ffs_i32(i32 signext %a) nounwind { +; CHECK-LABEL: ffs_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: addi a1, a0, -1 +; CHECK-NEXT: not a2, a0 +; CHECK-NEXT: and a1, a2, a1 +; CHECK-NEXT: li a2, 33 +; CHECK-NEXT: seqz a0, a0 +; CHECK-NEXT: clzw a1, a1 +; CHECK-NEXT: sub a2, a2, a1 +; CHECK-NEXT: addi a0, a0, -1 +; CHECK-NEXT: and a0, a0, a2 +; CHECK-NEXT: ret + %1 = call i32 @llvm.cttz.i32(i32 %a, i1 true) + %2 = add i32 %1, 1 + %3 = icmp eq i32 %a, 0 + %4 = select i1 %3, i32 0, i32 %2 + ret i32 %4 +} + +declare i64 @llvm.cttz.i64(i64, i1) + +define i64 @cttz_i64(i64 %a) nounwind { +; CHECK-LABEL: cttz_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: beqz a0, .LBB10_2 +; CHECK-NEXT: # %bb.1: # %cond.false +; CHECK-NEXT: addi a1, a0, -1 +; CHECK-NEXT: not a0, a0 +; CHECK-NEXT: and a0, a0, a1 +; CHECK-NEXT: clz a0, a0 +; CHECK-NEXT: li a1, 64 +; CHECK-NEXT: sub a0, a1, a0 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB10_2: +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: ret + %1 = call i64 @llvm.cttz.i64(i64 %a, i1 false) + ret i64 %1 +} + +define signext i32 @sextb_i32(i32 signext %a) nounwind { +; CHECK-LABEL: sextb_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: sext.b a0, a0 +; CHECK-NEXT: ret + %shl = shl i32 %a, 24 + %shr = ashr exact i32 %shl, 24 + ret i32 %shr +} + +define i64 @sextb_i64(i64 %a) nounwind { +; CHECK-LABEL: sextb_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: sext.b a0, a0 +; CHECK-NEXT: ret + %shl = shl i64 %a, 56 + %shr = ashr exact i64 %shl, 56 + ret i64 %shr +} + +define signext i32 @sexth_i32(i32 signext %a) nounwind { +; CHECK-LABEL: sexth_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: sext.h a0, a0 +; CHECK-NEXT: ret + %shl = shl i32 %a, 16 + %shr = ashr exact i32 %shl, 16 + ret i32 %shr +} + +define i64 @sexth_i64(i64 %a) nounwind { +; CHECK-LABEL: sexth_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: sext.h a0, a0 +; CHECK-NEXT: ret + %shl = shl i64 %a, 48 + %shr = ashr exact i64 %shl, 48 + ret i64 %shr +} + +define signext i32 @min_i32(i32 signext %a, i32 signext %b) nounwind { +; CHECK-LABEL: min_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: min a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp slt i32 %a, %b + %cond = select i1 %cmp, i32 %a, i32 %b + ret i32 %cond +} + +define i64 @min_i64(i64 %a, i64 %b) nounwind { +; CHECK-LABEL: min_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: min a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp slt i64 %a, %b + %cond = select i1 %cmp, i64 %a, i64 %b + ret i64 %cond +} + +define signext i32 @max_i32(i32 signext %a, i32 signext %b) nounwind { +; CHECK-LABEL: max_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: max a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp sgt i32 %a, %b + %cond = select i1 %cmp, i32 %a, i32 %b + ret i32 %cond +} + +define i64 @max_i64(i64 %a, i64 %b) nounwind { +; CHECK-LABEL: max_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: max a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp sgt i64 %a, %b + %cond = select i1 %cmp, i64 %a, i64 %b + ret i64 %cond +} + +define signext i32 @minu_i32(i32 signext %a, i32 signext %b) nounwind { +; CHECK-LABEL: minu_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: minu a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp ult i32 %a, %b + %cond = select i1 %cmp, i32 %a, i32 %b + ret i32 %cond +} + +define i64 @minu_i64(i64 %a, i64 %b) nounwind { +; CHECK-LABEL: minu_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: minu a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp ult i64 %a, %b + %cond = select i1 %cmp, i64 %a, i64 %b + ret i64 %cond +} + +define signext i32 @maxu_i32(i32 signext %a, i32 signext %b) nounwind { +; CHECK-LABEL: maxu_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: maxu a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp ugt i32 %a, %b + %cond = select i1 %cmp, i32 %a, i32 %b + ret i32 %cond +} + +define i64 @maxu_i64(i64 %a, i64 %b) nounwind { +; CHECK-LABEL: maxu_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: maxu a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp ugt i64 %a, %b + %cond = select i1 %cmp, i64 %a, i64 %b + ret i64 %cond +} + +declare i32 @llvm.abs.i32(i32, i1 immarg) + +define i32 @abs_i32(i32 %x) { +; CHECK-LABEL: abs_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: sext.w a0, a0 +; CHECK-NEXT: abs a0, a0 +; CHECK-NEXT: ret + %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) + ret i32 %abs +} + +define signext i32 @abs_i32_sext(i32 signext %x) { +; CHECK-LABEL: abs_i32_sext: +; CHECK: # %bb.0: +; CHECK-NEXT: abs a0, a0 +; CHECK-NEXT: sext.w a0, a0 +; CHECK-NEXT: ret + %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true) + ret i32 %abs +} + +declare i64 @llvm.abs.i64(i64, i1 immarg) + +define i64 @abs_i64(i64 %x) { +; CHECK-LABEL: abs_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: abs a0, a0 +; CHECK-NEXT: ret + %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true) + ret i64 %abs +} + +declare i32 @llvm.bswap.i32(i32) + +define signext i32 @bswap_i32(i32 signext %a) nounwind { +; CHECK-LABEL: bswap_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: rev8 a0, a0 +; CHECK-NEXT: srai a0, a0, 32 +; CHECK-NEXT: ret + %1 = tail call i32 @llvm.bswap.i32(i32 %a) + ret i32 %1 +} + +; Similar to bswap_i32 but the result is not sign extended. +define void @bswap_i32_nosext(i32 signext %a, ptr %x) nounwind { +; CHECK-LABEL: bswap_i32_nosext: +; CHECK: # %bb.0: +; CHECK-NEXT: rev8 a0, a0 +; CHECK-NEXT: srli a0, a0, 32 +; CHECK-NEXT: sw a0, 0(a1) +; CHECK-NEXT: ret + %1 = tail call i32 @llvm.bswap.i32(i32 %a) + store i32 %1, ptr %x + ret void +} + +declare i64 @llvm.bswap.i64(i64) + +define i64 @bswap_i64(i64 %a) { +; CHECK-LABEL: bswap_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: rev8 a0, a0 +; CHECK-NEXT: ret + %1 = call i64 @llvm.bswap.i64(i64 %a) + ret i64 %1 +} + +define i64 @srai_slli(i16 signext %0) { +; CHECK-LABEL: srai_slli: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a0, a0, 57 +; CHECK-NEXT: srai a0, a0, 63 +; CHECK-NEXT: ret + %2 = shl i16 %0, 9 + %sext = ashr i16 %2, 15 + %3 = sext i16 %sext to i64 + ret i64 %3 +} + +define i64 @srai_slli2(i16 signext %0) { +; CHECK-LABEL: srai_slli2: +; CHECK: # %bb.0: +; CHECK-NEXT: slli a0, a0, 57 +; CHECK-NEXT: srai a0, a0, 62 +; CHECK-NEXT: ret + %2 = shl i16 %0, 9 + %sext = ashr i16 %2, 14 + %3 = sext i16 %sext to i64 + ret i64 %3 +} + +define signext i32 @func0000000000000001(i32 signext %0, i8 signext %1) #0 { +; CHECK-LABEL: func0000000000000001: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: slli a1, a1, 59 +; CHECK-NEXT: srai a1, a1, 63 +; CHECK-NEXT: addw a0, a1, a0 +; CHECK-NEXT: ret +entry: + %2 = shl i8 %1, 3 + %3 = ashr i8 %2, 7 + %4 = sext i8 %3 to i32 + %5 = add nsw i32 %4, %0 + ret i32 %5 +} + +define i8 @sub_if_uge_i8(i8 %x, i8 %y) { +; CHECK-LABEL: sub_if_uge_i8: +; CHECK: # %bb.0: +; CHECK-NEXT: zext.b a2, a0 +; CHECK-NEXT: sub a0, a0, a1 +; CHECK-NEXT: zext.b a0, a0 +; CHECK-NEXT: minu a0, a2, a0 +; CHECK-NEXT: ret + %cmp = icmp ult i8 %x, %y + %select = select i1 %cmp, i8 0, i8 %y + %sub = sub nuw i8 %x, %select + ret i8 %sub +} + +define i16 @sub_if_uge_i16(i16 %x, i16 %y) { +; CHECK-LABEL: sub_if_uge_i16: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a2, 16 +; CHECK-NEXT: sub a1, a0, a1 +; CHECK-NEXT: addi a2, a2, -1 +; CHECK-NEXT: and a0, a0, a2 +; CHECK-NEXT: and a1, a1, a2 +; CHECK-NEXT: minu a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp ult i16 %x, %y + %select = select i1 %cmp, i16 0, i16 %y + %sub = sub nuw i16 %x, %select + ret i16 %sub +} + +define i32 @sub_if_uge_i32(i32 %x, i32 %y) { +; CHECK-LABEL: sub_if_uge_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: sext.w a2, a0 +; CHECK-NEXT: subw a0, a0, a1 +; CHECK-NEXT: minu a0, a2, a0 +; CHECK-NEXT: ret + %cmp = icmp ult i32 %x, %y + %select = select i1 %cmp, i32 0, i32 %y + %sub = sub nuw i32 %x, %select + ret i32 %sub +} + +define i64 @sub_if_uge_i64(i64 %x, i64 %y) { +; CHECK-LABEL: sub_if_uge_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: sub a1, a0, a1 +; CHECK-NEXT: minu a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp ult i64 %x, %y + %select = select i1 %cmp, i64 0, i64 %y + %sub = sub nuw i64 %x, %select + ret i64 %sub +} + +define i128 @sub_if_uge_i128(i128 %x, i128 %y) { +; CHECK-LABEL: sub_if_uge_i128: +; CHECK: # %bb.0: +; CHECK-NEXT: beq a1, a3, .LBB36_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: sltu a4, a1, a3 +; CHECK-NEXT: j .LBB36_3 +; CHECK-NEXT: .LBB36_2: +; CHECK-NEXT: sltu a4, a0, a2 +; CHECK-NEXT: .LBB36_3: +; CHECK-NEXT: addi a4, a4, -1 +; CHECK-NEXT: and a3, a4, a3 +; CHECK-NEXT: and a2, a4, a2 +; CHECK-NEXT: sltu a4, a0, a2 +; CHECK-NEXT: sub a1, a1, a3 +; CHECK-NEXT: sub a1, a1, a4 +; CHECK-NEXT: sub a0, a0, a2 +; CHECK-NEXT: ret + %cmp = icmp ult i128 %x, %y + %select = select i1 %cmp, i128 0, i128 %y + %sub = sub nuw i128 %x, %select + ret i128 %sub +} + +define i32 @sub_if_uge_multiuse_select_i32(i32 %x, i32 %y) { +; CHECK-LABEL: sub_if_uge_multiuse_select_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: sext.w a2, a1 +; CHECK-NEXT: sext.w a3, a0 +; CHECK-NEXT: sltu a2, a3, a2 +; CHECK-NEXT: addi a2, a2, -1 +; CHECK-NEXT: and a1, a2, a1 +; CHECK-NEXT: sub a0, a0, a1 +; CHECK-NEXT: sllw a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp ult i32 %x, %y + %select = select i1 %cmp, i32 0, i32 %y + %sub = sub nuw i32 %x, %select + %shl = shl i32 %sub, %select + ret i32 %shl +} + +define i32 @sub_if_uge_multiuse_cmp_i32(i32 %x, i32 %y) { +; CHECK-LABEL: sub_if_uge_multiuse_cmp_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: sext.w a2, a1 +; CHECK-NEXT: sext.w a3, a0 +; CHECK-NEXT: subw a0, a0, a1 +; CHECK-NEXT: minu a0, a3, a0 +; CHECK-NEXT: bltu a3, a2, .LBB38_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: li a1, 4 +; CHECK-NEXT: sllw a0, a0, a1 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB38_2: +; CHECK-NEXT: li a1, 2 +; CHECK-NEXT: sllw a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp ult i32 %x, %y + %select = select i1 %cmp, i32 0, i32 %y + %sub = sub nuw i32 %x, %select + %select2 = select i1 %cmp, i32 2, i32 4 + %shl = shl i32 %sub, %select2 + ret i32 %shl +} + +define i32 @sub_if_uge_multiuse_cmp_store_i32(i32 signext %x, i32 signext %y, ptr %z) { +; CHECK-LABEL: sub_if_uge_multiuse_cmp_store_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: sltu a3, a0, a1 +; CHECK-NEXT: subw a1, a0, a1 +; CHECK-NEXT: xori a3, a3, 1 +; CHECK-NEXT: minu a0, a0, a1 +; CHECK-NEXT: sw a3, 0(a2) +; CHECK-NEXT: ret + %cmp = icmp uge i32 %x, %y + %conv = zext i1 %cmp to i32 + store i32 %conv, ptr %z, align 4 + %select = select i1 %cmp, i32 %y, i32 0 + %sub = sub nuw i32 %x, %select + ret i32 %sub +} + +define i8 @sub_if_uge_C_i8(i8 zeroext %x) { +; CHECK-LABEL: sub_if_uge_C_i8: +; CHECK: # %bb.0: +; CHECK-NEXT: addi a1, a0, -13 +; CHECK-NEXT: zext.b a1, a1 +; CHECK-NEXT: minu a0, a1, a0 +; CHECK-NEXT: ret + %cmp = icmp ugt i8 %x, 12 + %sub = add i8 %x, -13 + %conv4 = select i1 %cmp, i8 %sub, i8 %x + ret i8 %conv4 +} + +define i16 @sub_if_uge_C_i16(i16 zeroext %x) { +; CHECK-LABEL: sub_if_uge_C_i16: +; CHECK: # %bb.0: +; CHECK-NEXT: addi a1, a0, -251 +; CHECK-NEXT: slli a1, a1, 48 +; CHECK-NEXT: srli a1, a1, 48 +; CHECK-NEXT: minu a0, a1, a0 +; CHECK-NEXT: ret + %cmp = icmp ugt i16 %x, 250 + %sub = add i16 %x, -251 + %conv4 = select i1 %cmp, i16 %sub, i16 %x + ret i16 %conv4 +} + +define i32 @sub_if_uge_C_i32(i32 signext %x) { +; CHECK-LABEL: sub_if_uge_C_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a1, 1048560 +; CHECK-NEXT: addi a1, a1, 15 +; CHECK-NEXT: addw a1, a0, a1 +; CHECK-NEXT: minu a0, a1, a0 +; CHECK-NEXT: ret + %cmp = icmp ugt i32 %x, 65520 + %sub = add i32 %x, -65521 + %cond = select i1 %cmp, i32 %sub, i32 %x + ret i32 %cond +} + +define i64 @sub_if_uge_C_i64(i64 %x) { +; CHECK-LABEL: sub_if_uge_C_i64: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a1, 1046192 +; CHECK-NEXT: addi a1, a1, -761 +; CHECK-NEXT: slli a1, a1, 9 +; CHECK-NEXT: add a1, a0, a1 +; CHECK-NEXT: minu a0, a1, a0 +; CHECK-NEXT: ret + %cmp = icmp ugt i64 %x, 4999999999 + %sub = add i64 %x, -5000000000 + %cond = select i1 %cmp, i64 %sub, i64 %x + ret i64 %cond +} + +define i32 @sub_if_uge_C_multiuse_cmp_i32(i32 signext %x, ptr %z) { +; CHECK-LABEL: sub_if_uge_C_multiuse_cmp_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a2, 16 +; CHECK-NEXT: lui a3, 1048560 +; CHECK-NEXT: addi a2, a2, -16 +; CHECK-NEXT: addi a3, a3, 15 +; CHECK-NEXT: sltu a2, a2, a0 +; CHECK-NEXT: addw a3, a0, a3 +; CHECK-NEXT: minu a0, a3, a0 +; CHECK-NEXT: sw a2, 0(a1) +; CHECK-NEXT: ret + %cmp = icmp ugt i32 %x, 65520 + %conv = zext i1 %cmp to i32 + store i32 %conv, ptr %z, align 4 + %sub = add i32 %x, -65521 + %cond = select i1 %cmp, i32 %sub, i32 %x + ret i32 %cond +} + +define i32 @sub_if_uge_C_multiuse_sub_i32(i32 signext %x, ptr %z) { +; CHECK-LABEL: sub_if_uge_C_multiuse_sub_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a2, 1048560 +; CHECK-NEXT: addi a2, a2, 15 +; CHECK-NEXT: addw a2, a0, a2 +; CHECK-NEXT: minu a0, a2, a0 +; CHECK-NEXT: sw a2, 0(a1) +; CHECK-NEXT: ret + %sub = add i32 %x, -65521 + store i32 %sub, ptr %z, align 4 + %cmp = icmp ugt i32 %x, 65520 + %cond = select i1 %cmp, i32 %sub, i32 %x + ret i32 %cond +} + +define i32 @sub_if_uge_C_swapped_i32(i32 signext %x) { +; CHECK-LABEL: sub_if_uge_C_swapped_i32: +; CHECK: # %bb.0: +; CHECK-NEXT: lui a1, 1048560 +; CHECK-NEXT: addi a1, a1, 15 +; CHECK-NEXT: addw a1, a0, a1 +; CHECK-NEXT: minu a0, a0, a1 +; CHECK-NEXT: ret + %cmp = icmp ult i32 %x, 65521 + %sub = add i32 %x, -65521 + %cond = select i1 %cmp, i32 %x, i32 %sub + ret i32 %cond +} + +define i7 @sub_if_uge_C_nsw_i7(i7 %a) { +; CHECK-LABEL: sub_if_uge_C_nsw_i7: +; CHECK: # %bb.0: +; CHECK-NEXT: ori a0, a0, 51 +; CHECK-NEXT: andi a1, a0, 127 +; CHECK-NEXT: addi a0, a0, 17 +; CHECK-NEXT: andi a0, a0, 92 +; CHECK-NEXT: minu a0, a0, a1 +; CHECK-NEXT: ret + %x = or i7 %a, 51 + %c = icmp ugt i7 %x, -18 + %add = add nsw i7 %x, 17 + %s = select i1 %c, i7 %add, i7 %x + ret i7 %s +} + +define i7 @sub_if_uge_C_swapped_nsw_i7(i7 %a) { +; CHECK-LABEL: sub_if_uge_C_swapped_nsw_i7: +; CHECK: # %bb.0: +; CHECK-NEXT: ori a0, a0, 51 +; CHECK-NEXT: andi a1, a0, 127 +; CHECK-NEXT: addi a0, a0, 17 +; CHECK-NEXT: andi a0, a0, 92 +; CHECK-NEXT: minu a0, a1, a0 +; CHECK-NEXT: ret + %x = or i7 %a, 51 + %c = icmp ult i7 %x, -17 + %add = add nsw i7 %x, 17 + %s = select i1 %c, i7 %x, i7 %add + ret i7 %s +} diff --git a/llvm/test/CodeGen/X86/issue163738.ll b/llvm/test/CodeGen/X86/issue163738.ll new file mode 100644 index 0000000..61fe043 --- /dev/null +++ b/llvm/test/CodeGen/X86/issue163738.ll @@ -0,0 +1,13 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6 +; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx512f,+avx512vl | FileCheck %s --check-prefixes=CHECK + +define <8 x i64> @foo(<8 x i64> %a, <8 x i64> %b, <8 x i64> %c) { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: +; CHECK-NEXT: vpternlogq {{.*#+}} zmm0 = ~(zmm0 | zmm2 | zmm1) +; CHECK-NEXT: retq + %and.demorgan = or <8 x i64> %b, %a + %and3.demorgan = or <8 x i64> %and.demorgan, %c + %and3 = xor <8 x i64> %and3.demorgan, splat (i64 -1) + ret <8 x i64> %and3 +} |