diff options
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
| -rw-r--r-- | llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 10 |
1 files changed, 2 insertions, 8 deletions
diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 0994901..716299a 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -527,8 +527,8 @@ static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm, uint64_t Address, const MCDisassembler *Decoder); -static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm, - uint64_t Address, const void *Decoder); +static DecodeStatus decodeZcmpStackAdj(MCInst &Inst, uint32_t Imm, + uint64_t Address, const void *Decoder); static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, uint64_t Address, @@ -668,12 +668,6 @@ static DecodeStatus decodeXqccmpRlistS0(MCInst &Inst, uint32_t Imm, return MCDisassembler::Success; } -static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm, - uint64_t Address, const void *Decoder) { - Inst.addOperand(MCOperand::createImm(Imm)); - return MCDisassembler::Success; -} - // Add implied SP operand for C.*SP compressed instructions. The SP operand // isn't explicitly encoded in the instruction. void RISCVDisassembler::addSPOperands(MCInst &MI) const { |