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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2023-06-24 06:56:01 -0400 |
|---|---|---|
| committer | Matt Arsenault <Matthew.Arsenault@amd.com> | 2023-06-26 13:58:06 -0400 |
| commit | fe0750b97943070c4dc652afa3628aee0b0d0ebb (patch) | |
| tree | 1a9558846929cac727321b7394aee04944d27cdc /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 249bd9eab0aa122453073278bb9cd53f73c08cf8 (diff) | |
| download | llvm-fe0750b97943070c4dc652afa3628aee0b0d0ebb.zip llvm-fe0750b97943070c4dc652afa3628aee0b0d0ebb.tar.gz llvm-fe0750b97943070c4dc652afa3628aee0b0d0ebb.tar.bz2 | |
SeparateConstOffsetFromGEP: Reorder run lines
Testing codegen in test/Transforms is questionable to begin with, but
it's more reasonable to see failures on the IR half before ISA checks.
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions