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| author | Maurice Heumann <MauriceHeumann@gmail.com> | 2023-06-26 09:41:31 -0700 |
|---|---|---|
| committer | Eli Friedman <efriedma@quicinc.com> | 2023-06-26 10:45:41 -0700 |
| commit | 249bd9eab0aa122453073278bb9cd53f73c08cf8 (patch) | |
| tree | d253af3f4d22c9201c25e8ba1bdd20febd2cd028 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | bc7f11ccb01cbc2ae6c1631535ea5c181f70cb1e (diff) | |
| download | llvm-249bd9eab0aa122453073278bb9cd53f73c08cf8.zip llvm-249bd9eab0aa122453073278bb9cd53f73c08cf8.tar.gz llvm-249bd9eab0aa122453073278bb9cd53f73c08cf8.tar.bz2 | |
[ARM] Fix codegen of unaligned volatile load/store of i64
Volatile loads/stores of i64 are lowered to LDRD/STRD on ARMv5TE.
However, these instructions require the addresses to be aligned.
Unaligned loads/stores therefore should be ignored by this handling.
Differential Revision: https://reviews.llvm.org/D152790
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions