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| author | WuXinlong <821408745@qq.com> | 2023-06-21 15:40:33 +0800 |
|---|---|---|
| committer | WuXinlong <821408745@qq.com> | 2023-06-21 15:41:51 +0800 |
| commit | c9e08fa6066649d96cff8c20da42eb0b44dc878b (patch) | |
| tree | b9248495c1e8cc4e3af2cd7929966579a9462421 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 42a82b1ac6c834b7ce9766db22d169bd81415d52 (diff) | |
| download | llvm-c9e08fa6066649d96cff8c20da42eb0b44dc878b.zip llvm-c9e08fa6066649d96cff8c20da42eb0b44dc878b.tar.gz llvm-c9e08fa6066649d96cff8c20da42eb0b44dc878b.tar.bz2 | |
[RISCV] Add a pass to merge moving parameter registers instructions for Zcmp
This patch adds a pass to generate `cm.mvsa01` & `cm.mva01s`.
RISCVMoveOptimizer.cpp which combines two mv inst into one cm.mva01s or cm.mva01s.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D150415
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions