From c4645ffedacad18e4cd1dd372288aa55178b1c44 Mon Sep 17 00:00:00 2001 From: Sudharsan Veeravalli Date: Thu, 28 Nov 2024 12:46:15 +0530 Subject: [RISCV] Add Qualcomm uC Xqcicsr (CSR) extension (#117169) The Qualcomm uC Xqcicsr extension adds 2 instructions that can read and write CSRs. The current spec can be found at: https://github.com/quic/riscv-unified-db/releases/latest This patch adds assembler only support. --- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 2 ++ 1 file changed, 2 insertions(+) (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp') diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index cf8e337..e4f7ee3 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -682,6 +682,8 @@ DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size, "CORE-V SIMD extensions custom opcode table"); TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32, "CORE-V Immediate Branching custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXqcicsr, DecoderTableXqcicsr32, + "Qualcomm uC CSR custom opcode table"); TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); return MCDisassembler::Fail; -- cgit v1.1