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| author | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2023-02-03 15:21:31 -0800 |
|---|---|---|
| committer | Stanislav Mekhanoshin <Stanislav.Mekhanoshin@amd.com> | 2023-02-05 12:21:28 -0800 |
| commit | dd0caa82de593f080469c772b5b092e1bf7f7cc0 (patch) | |
| tree | a8b311461377bf4559e73d0921b8dfab22fe79b6 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | f9bf64798c1aee3d9f1ce754b2d625026e29d197 (diff) | |
| download | llvm-dd0caa82de593f080469c772b5b092e1bf7f7cc0.zip llvm-dd0caa82de593f080469c772b5b092e1bf7f7cc0.tar.gz llvm-dd0caa82de593f080469c772b5b092e1bf7f7cc0.tar.bz2 | |
[AMDGPU] Fix liveness in the SIOptimizeExecMaskingPreRA.cpp
If a condition register def happens past the newly created use
we do not properly update LIS. It has two problems:
1) We do not extend defining segment to the end of its block
marking it a live-out (this is regression after
https://reviews.llvm.org/rG09d38dd7704a52e8ad2d5f8f39aaeccf107f4c56)
2) We do not extend use segment to the beginning of the use block
marking it a live-in.
Fixes: SWDEV-379563
Differential Revision: https://reviews.llvm.org/D143302
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions