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| author | Sergei Barannikov <barannikov88@gmail.com> | 2023-05-24 08:02:50 +0300 |
|---|---|---|
| committer | Sergei Barannikov <barannikov88@gmail.com> | 2023-05-25 06:33:41 +0300 |
| commit | 4374026d6da23dbb6b9c2e4fca65cdf198ee1e0f (patch) | |
| tree | 24acbfa375a94df11c571e82ddaad44fd197a94b /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 0f3efb8d7f3f0c96c82a98c12d2a26404116cc56 (diff) | |
| download | llvm-4374026d6da23dbb6b9c2e4fca65cdf198ee1e0f.zip llvm-4374026d6da23dbb6b9c2e4fca65cdf198ee1e0f.tar.gz llvm-4374026d6da23dbb6b9c2e4fca65cdf198ee1e0f.tar.bz2 | |
[MIPS] Check if register is non-null before calling isSuperOrSubRegisterEq (NFCI)
D151036 adds an assertions that prohibits iterating over sub- and
super-registers of a null register. This is already the case when
iterating over register units of a null register, and worked by
accident for sub- and super-registers.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D151288
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions