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| author | Stefan Pintilie <stefanp@ca.ibm.com> | 2023-02-13 09:59:23 -0500 |
|---|---|---|
| committer | Stefan Pintilie <stefanp@ca.ibm.com> | 2023-02-13 10:18:53 -0500 |
| commit | 2e47aafb02f3e46fc3e01799053e01835239151d (patch) | |
| tree | e0b68d147a1472cf4bccff80ac99f80b2abeb677 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | 6a6c527ee287a4a7787fb5c519014c2e22f718c3 (diff) | |
| download | llvm-2e47aafb02f3e46fc3e01799053e01835239151d.zip llvm-2e47aafb02f3e46fc3e01799053e01835239151d.tar.gz llvm-2e47aafb02f3e46fc3e01799053e01835239151d.tar.bz2 | |
[PowerPC] Fix float materialization patterns.
Two of the float materialization patterns use the VSSRC regsiter class. This
register class is not available before Power 8. The patterns will stay the same
for Power 8 and up but must use the class F4RC for Power 7 and earlier.
This patch fixes those patterns.
Reviewed By: nemanjai, amyk, #powerpc
Differential Revision: https://reviews.llvm.org/D142120
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions