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| author | Matt Arsenault <Matthew.Arsenault@amd.com> | 2025-05-21 17:00:45 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2025-05-21 17:00:45 +0200 |
| commit | 2e2bbcacf813de52f6e7f48dea67e26de1f1f99e (patch) | |
| tree | d7becb54b30f6a23b98da9fa28025f121589cf81 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | |
| parent | b263c08e1a0b54a871915930aa9a1a6ba205b099 (diff) | |
| download | llvm-2e2bbcacf813de52f6e7f48dea67e26de1f1f99e.zip llvm-2e2bbcacf813de52f6e7f48dea67e26de1f1f99e.tar.gz llvm-2e2bbcacf813de52f6e7f48dea67e26de1f1f99e.tar.bz2 | |
AMDGPU/GlobalISel: Start legalizing minimumnum and maximumnum (#140900)
This is the bare minimum to get the intrinsic to compile for AMDGPU,
and it's not optimal. We need to follow along closer with the existing
G_FMINNUM/G_FMAXNUM with custom lowering to handle the IEEE=0 case
better.
Just re-use the existing lowering for the old semantics for
G_FMINNUM/G_FMAXNUM. This does not change G_FMINNUM/G_FMAXNUM's
treatment,
nor try to handle the general expansion without an underlying min/max
variant (or with G_FMINIMUM/G_FMAXIMUM).
Diffstat (limited to 'llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp')
0 files changed, 0 insertions, 0 deletions