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authorFlorian Hahn <flo@fhahn.com>2025-05-21 15:47:33 +0100
committerGitHub <noreply@github.com>2025-05-21 15:47:33 +0100
commitb263c08e1a0b54a871915930aa9a1a6ba205b099 (patch)
tree7cd0600c7fdf557dcf6cb51c3497facd78271598 /llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp
parentdabc84c890e5817d9c85df04bcaa279ecfd44a3c (diff)
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[VPlan] Move predication to VPlanTransform (NFC). (#128420)
This patch moves the logic to predicate and linearize a VPlan to a dedicated VPlan transform. It mostly ports the existing logic directly. There are a number of follow-ups planned in the near future to further improve on the implementation: * Edge and block masks are cached in VPPredicator, but the block masks are still made available to VPRecipeBuilder, so they can be accessed during recipe construction. As a follow-up, this should be replaced by adding mask operands to all VPInstructions that need them and use that during recipe construction. * The mask caching in a map also means that this map needs updating each time a new recipe replaces a VPInstruction; this would also be handled by adding mask operands. PR: https://github.com/llvm/llvm-project/pull/128420
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