aboutsummaryrefslogtreecommitdiff
path: root/sim/m32r
AgeCommit message (Expand)AuthorFilesLines
2024-01-12Update copyright year range in header of all files managed by GDBAndrew Burgess36-36/+36
2024-01-10sim: m32r: enable warnings in traps.cMike Frysinger1-3/+0
2024-01-10sim: m32r: fixup some of the int<->pointer castsMike Frysinger1-28/+53
2024-01-10sim: m32r: fix missing break statementMike Frysinger1-0/+1
2024-01-10sim: m32r: migrate ftime() to clock_gettime()Mike Frysinger1-5/+8
2024-01-10sim: m32r: cleanup unused variablesMike Frysinger1-3/+1
2024-01-08sim: build: clean more generated outputsMike Frysinger1-0/+1
2023-12-24sim: cgen: regenerate decode tablesMike Frysinger3-705/+705
2023-12-22sim: cgen: regenerate decode tables to avoid shadow warningsMike Frysinger3-60/+60
2023-12-21sim: mloop: add #line pragmas everywhereMike Frysinger3-0/+10
2023-12-21sim: signal: mark signal callback funcs as noreturn since they don't returnMike Frysinger1-1/+1
2023-12-20sim: cgen: unify the genmloop logic a bitMike Frysinger1-12/+9
2023-12-19sim: m32r: fix -Wunused-variable warningsMike Frysinger1-2/+0
2023-12-14sim: m32r: fix mloop.in variant stamp depsMike Frysinger1-2/+2
2023-12-14sim: m32r: use @cpu@_fill_argbuf_tp to set trace & profile stateMike Frysinger2-16/+8
2023-12-07sim: m32r: fix syslog callMike Frysinger1-1/+2
2023-12-07sim: m32r: include more glibc headers for the funcs we use [PR sim/29752]Mike Frysinger1-0/+5
2023-12-07sim: m32r: add more cgen prototypes for trapsMike Frysinger1-0/+12
2023-12-07sim: m32r: add more cgen prototypes to enable -Werror in most filesMike Frysinger2-13/+27
2023-08-19sim regenAlan Modra22-84/+120
2023-08-19sim --enable-cgen-maintAlan Modra1-4/+4
2023-01-18sim: info: convert verbose field to a boolMike Frysinger1-2/+2
2023-01-15sim: modules.c: fix generation after recent refactorsMike Frysinger1-0/+3
2023-01-15sim: m32r: fix typos in stamp dependsMike Frysinger1-2/+2
2023-01-14sim: common: move modules.c to source trackingMike Frysinger1-1/+2
2023-01-14sim: build: drop most recursive build depsMike Frysinger1-2/+1
2023-01-14sim: common: move libcommon.a objects to sourcesMike Frysinger1-2/+2
2023-01-14sim: build: drop AM_MAKEFLAGS settingsMike Frysinger1-1/+0
2023-01-11sim: build: drop subdir Makefile.in filesMike Frysinger1-24/+0
2023-01-10sim: move arch-specific file compilation of common/ files to top-levelMike Frysinger1-2/+2
2023-01-10sim: m32r: move arch-specific file compilation to top-levelMike Frysinger2-6/+14
2023-01-10sim: build: drop support for creating libsim.a in subdirsMike Frysinger1-2/+0
2023-01-10sim: m32r: move libsim.a creation to top-levelMike Frysinger2-13/+47
2023-01-10sim: modules: trigger generation from top-levelMike Frysinger1-0/+1
2023-01-02sim: build: move generated headers to built sourcesMike Frysinger1-3/+5
2023-01-02sim: m32r: hoist cgen rules to top-levelMike Frysinger2-48/+19
2023-01-01sim: replace -I$srcroot/opcodes include with -I$srcrootMike Frysinger1-2/+2
2023-01-01Update copyright year range in header of all files managed by GDBJoel Brobecker37-37/+37
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-25sim: m32r: fix iterator typo when setting up cpusMike Frysinger1-1/+1
2022-12-23sim: m32r: move arch-specific settings to internal headerMike Frysinger7-22/+33
2022-12-23sim: lm32/m32r: drop redundant opcode/cgen.h includeMike Frysinger1-1/+0
2022-12-23sim: cgen: move symcat.h include to where it's usedMike Frysinger2-1/+2
2022-12-23sim: cgen: move cgen-types.h include to cgen-defs.hMike Frysinger1-1/+0
2022-12-22sim: use bfd_vma when reading start addr from bfd infoMike Frysinger1-1/+1
2022-12-22sim: m32r: include sim-hw.h for sim_hw_parseMike Frysinger1-0/+1
2022-12-21sim: build: hoist lists of hw devices upMike Frysinger2-4/+5
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger1-2/+0
2022-12-21sim: m32r: invert sim_cpu storageMike Frysinger5-14/+10
2022-11-05sim: run: move linking into top-levelMike Frysinger1-0/+8
generated by cgit v1.1 at 2024-11-03 23:32:20 +0000