sim: cgen: regenerate decode tables to avoid shadow warnings

Use latest cgen to regenerate the decode tables which has some shadow
warning fixes with "val" variables.

3 files changed, 60 insertions, 60 deletions

diff --git a/sim/m32r/decode.c b/sim/m32r/decode.c
index 7d802a3..dae456d 100644
--- a/sim/m32r/decode.c
+++ b/sim/m32r/decode.c
@@ -229,8 +229,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
     CGEN_INSN_WORD insn = base_insn;
 
     {
-      unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
-      switch (val)
+      unsigned int val0 = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
+      switch (val0)
       {
       case 0 : itype = M32RBF_INSN_SUBV; goto extract_sfmt_addv;
       case 1 : itype = M32RBF_INSN_SUBX; goto extract_sfmt_addx;
@@ -258,8 +258,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 26 : itype = M32RBF_INSN_MVTC; goto extract_sfmt_mvtc;
       case 28 :
         {
-          unsigned int val = (((insn >> 8) & (1 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 8) & (1 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xfff0) == 0x1ec0)
@@ -325,8 +325,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 85 : itype = M32RBF_INSN_SLLI; goto extract_sfmt_slli;
       case 87 :
         {
-          unsigned int val = (((insn >> 0) & (1 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 0) & (1 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xf0ff) == 0x5070)
@@ -349,8 +349,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
         itype = M32RBF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 95 :
         {
-          unsigned int val = (((insn >> 0) & (3 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 0) & (3 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xf0ff) == 0x50f0)
@@ -385,8 +385,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 111 : itype = M32RBF_INSN_LDI8; goto extract_sfmt_ldi8;
       case 112 :
         {
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 8) & (15 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xffff) == 0x7000)
@@ -417,8 +417,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 126 : /* fall through */
       case 127 :
         {
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 8) & (15 << 0)));
+          switch (val1)
           {
           case 1 : itype = M32RBF_INSN_SETPSW; goto extract_sfmt_setpsw;
           case 2 : itype = M32RBF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
@@ -544,8 +544,8 @@ m32rbf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 254 : /* fall through */
       case 255 :
         {
-          unsigned int val = (((insn >> 8) & (3 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 8) & (3 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xff000000) == 0xfc000000)
diff --git a/sim/m32r/decode2.c b/sim/m32r/decode2.c
index 60909af..c8677e6 100644
--- a/sim/m32r/decode2.c
+++ b/sim/m32r/decode2.c
@@ -272,8 +272,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
     CGEN_INSN_WORD insn = base_insn;
 
     {
-      unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
-      switch (val)
+      unsigned int val0 = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
+      switch (val0)
       {
       case 0 : itype = M32R2F_INSN_SUBV; goto extract_sfmt_addv;
       case 1 : itype = M32R2F_INSN_SUBX; goto extract_sfmt_addx;
@@ -284,8 +284,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
       case 6 : itype = M32R2F_INSN_CMPEQ; goto extract_sfmt_cmp;
       case 7 :
         {
-          unsigned int val = (((insn >> 8) & (3 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 8) & (3 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xfff0) == 0x70)
@@ -318,8 +318,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
       case 26 : itype = M32R2F_INSN_MVTC; goto extract_sfmt_mvtc;
       case 28 :
         {
-          unsigned int val = (((insn >> 8) & (3 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 8) & (3 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xfff0) == 0x1cc0)
@@ -403,8 +403,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
       case 85 : itype = M32R2F_INSN_SLLI; goto extract_sfmt_slli;
       case 87 :
         {
-          unsigned int val = (((insn >> 0) & (1 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 0) & (1 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xf0f3) == 0x5070)
@@ -435,8 +435,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
         itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
       case 95 :
         {
-          unsigned int val = (((insn >> 0) & (3 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 0) & (3 << 0)));
+          switch (val1)
           {
           case 0 : itype = M32R2F_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a;
           case 1 : itype = M32R2F_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a;
@@ -462,8 +462,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
       case 111 : itype = M32R2F_INSN_LDI8; goto extract_sfmt_ldi8;
       case 112 :
         {
-          unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xffff) == 0x7000)
@@ -512,8 +512,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
       case 126 : /* fall through */
       case 127 :
         {
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 8) & (15 << 0)));
+          switch (val1)
           {
           case 1 : itype = M32R2F_INSN_SETPSW; goto extract_sfmt_setpsw;
           case 2 : itype = M32R2F_INSN_CLRPSW; goto extract_sfmt_clrpsw;
@@ -536,8 +536,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
         itype = M32R2F_INSN_X_INVALID; goto extract_sfmt_empty;
       case 134 :
         {
-          unsigned int val = (((entire_insn >> 8) & (3 << 0)));
-          switch (val)
+          unsigned int val1 = (((entire_insn >> 8) & (3 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xf0f0ffff) == 0x80600000)
@@ -561,8 +561,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
       case 142 : itype = M32R2F_INSN_OR3; goto extract_sfmt_or3;
       case 144 :
         {
-          unsigned int val = (((entire_insn >> 3) & (3 << 0)));
-          switch (val)
+          unsigned int val1 = (((entire_insn >> 3) & (3 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xf0f0ffff) == 0x90000000)
@@ -581,8 +581,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
         }
       case 145 :
         {
-          unsigned int val = (((entire_insn >> 3) & (3 << 0)));
-          switch (val)
+          unsigned int val1 = (((entire_insn >> 3) & (3 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xf0f0ffff) == 0x90100000)
@@ -601,8 +601,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
         }
       case 146 :
         {
-          unsigned int val = (((entire_insn >> 3) & (3 << 0)));
-          switch (val)
+          unsigned int val1 = (((entire_insn >> 3) & (3 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xf0f0ffff) == 0x90200000)
@@ -621,8 +621,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
         }
       case 147 :
         {
-          unsigned int val = (((entire_insn >> 3) & (3 << 0)));
-          switch (val)
+          unsigned int val1 = (((entire_insn >> 3) & (3 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xf0f0ffff) == 0x90300000)
@@ -725,8 +725,8 @@ m32r2f_decode (SIM_CPU *current_cpu, IADDR pc,
       case 254 : /* fall through */
       case 255 :
         {
-          unsigned int val = (((insn >> 8) & (7 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 8) & (7 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xff000000) == 0xf8000000)
diff --git a/sim/m32r/decodex.c b/sim/m32r/decodex.c
index ad2c3f0..864ea82 100644
--- a/sim/m32r/decodex.c
+++ b/sim/m32r/decodex.c
@@ -265,8 +265,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
     CGEN_INSN_WORD insn = base_insn;
 
     {
-      unsigned int val = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
-      switch (val)
+      unsigned int val0 = (((insn >> 8) & (15 << 4)) | ((insn >> 4) & (15 << 0)));
+      switch (val0)
       {
       case 0 : itype = M32RXF_INSN_SUBV; goto extract_sfmt_addv;
       case 1 : itype = M32RXF_INSN_SUBX; goto extract_sfmt_addx;
@@ -277,8 +277,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 6 : itype = M32RXF_INSN_CMPEQ; goto extract_sfmt_cmp;
       case 7 :
         {
-          unsigned int val = (((insn >> 8) & (3 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 8) & (3 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xfff0) == 0x70)
@@ -311,8 +311,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 26 : itype = M32RXF_INSN_MVTC; goto extract_sfmt_mvtc;
       case 28 :
         {
-          unsigned int val = (((insn >> 8) & (3 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 8) & (3 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xfff0) == 0x1cc0)
@@ -396,8 +396,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 85 : itype = M32RXF_INSN_SLLI; goto extract_sfmt_slli;
       case 87 :
         {
-          unsigned int val = (((insn >> 0) & (1 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 0) & (1 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xf0f3) == 0x5070)
@@ -428,8 +428,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
         itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 95 :
         {
-          unsigned int val = (((insn >> 0) & (3 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 0) & (3 << 0)));
+          switch (val1)
           {
           case 0 : itype = M32RXF_INSN_MVFACHI_A; goto extract_sfmt_mvfachi_a;
           case 1 : itype = M32RXF_INSN_MVFACLO_A; goto extract_sfmt_mvfachi_a;
@@ -455,8 +455,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 111 : itype = M32RXF_INSN_LDI8; goto extract_sfmt_ldi8;
       case 112 :
         {
-          unsigned int val = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 7) & (15 << 1)) | ((insn >> 0) & (1 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xffff) == 0x7000)
@@ -505,8 +505,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 126 : /* fall through */
       case 127 :
         {
-          unsigned int val = (((insn >> 8) & (15 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 8) & (15 << 0)));
+          switch (val1)
           {
           case 1 : itype = M32RXF_INSN_SETPSW; goto extract_sfmt_setpsw;
           case 2 : itype = M32RXF_INSN_CLRPSW; goto extract_sfmt_clrpsw;
@@ -529,8 +529,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
         itype = M32RXF_INSN_X_INVALID; goto extract_sfmt_empty;
       case 134 :
         {
-          unsigned int val = (((entire_insn >> 8) & (3 << 0)));
-          switch (val)
+          unsigned int val1 = (((entire_insn >> 8) & (3 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xf0f0ffff) == 0x80600000)
@@ -554,8 +554,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 142 : itype = M32RXF_INSN_OR3; goto extract_sfmt_or3;
       case 144 :
         {
-          unsigned int val = (((entire_insn >> 4) & (1 << 0)));
-          switch (val)
+          unsigned int val1 = (((entire_insn >> 4) & (1 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xf0f0ffff) == 0x90000000)
@@ -666,8 +666,8 @@ m32rxf_decode (SIM_CPU *current_cpu, IADDR pc,
       case 254 : /* fall through */
       case 255 :
         {
-          unsigned int val = (((insn >> 8) & (7 << 0)));
-          switch (val)
+          unsigned int val1 = (((insn >> 8) & (7 << 0)));
+          switch (val1)
           {
           case 0 :
             if ((entire_insn & 0xff000000) == 0xf8000000)