| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2000-01-06 | import gdb-2000-01-05 snapshot | Jason Molenda | 4 | -27/+200 |
| 1999-12-07 | import gdb-1999-12-06 snapshot | Jason Molenda | 2 | -0/+27 |
| 1999-11-17 | import gdb-1999-11-16 snapshot | Jason Molenda | 4 | -312/+707 |
| 1999-11-02 | import gdb-1999-11-01 snapshot | Jason Molenda | 2 | -2/+7 |
| 1999-09-22 | import gdb-1999-09-21 | Jason Molenda | 2 | -7/+5 |
| 1999-09-13 | import gdb-1999-09-13 snapshot | Jason Molenda | 3 | -20/+272 |
| 1999-09-09 | import gdb-1999-09-08 snapshot | Stan Shebs | 3 | -160/+176 |
| 1999-05-11 | import gdb-1999-05-10 | Stan Shebs | 2 | -174/+308 |
| 1999-04-26 | import gdb-19990422 snapshot | Stan Shebs | 4 | -2/+46 |
| 1999-04-16 | Initial creation of sourceware repositorygdb-4_18-branchpoint | Stan Shebs | 11 | -0/+10212 |
| 1999-04-16 | Initial creation of sourceware repository | Stan Shebs | 12 | -9576/+0 |
| 1999-01-27 | 1999-01-26 Jason Molenda (jsm@bugshack.cygnus.com) | Jason Molenda | 2 | -868/+1058 |
| 1998-09-30 | Fix PR 17387: ignore auto increment for loads where the destination register | Nick Clifton | 1 | -0/+10 |
| 1998-04-26 | * configure: Regenerated to track ../common/aclocal.m4 changes. | Tom Tromey | 5 | -120/+148 |
| 1998-04-24 | * configure: Regenerated to track ../common/aclocal.m4 changes. | Tom Tromey | 3 | -39/+1786 |
| 1998-04-24 | * interp.c (struct hash_entry): OPCODE and MASK are unsigned. | Andrew Cagney | 1 | -0/+57 |
| 1998-04-01 | * configure.in (SIM_AC_OPTION_WARNINGS): Add. | Andrew Cagney | 2 | -0/+8 |
| 1998-03-27 | Do top level sim-hw module for device tree. | Andrew Cagney | 2 | -34/+136 |
| 1998-02-16 | Implement "dbt" and "rtd" instructions. | Andrew Cagney | 2 | -15/+40 |
| 1998-02-13 | Implement separate user (SPU) and interrupt (SPI) stack pointers. | Andrew Cagney | 3 | -0/+15 |
| 1998-02-11 | Don't abort() when system call is unknown. | Andrew Cagney | 2 | -1/+4 |
| 1998-02-11 | Ensure zero-hardwired bits in DPSW remain zero. | Andrew Cagney | 3 | -4/+77 |
| 1998-02-10 | D10v memory map changed. Update. | Andrew Cagney | 1 | -136/+173 |
| 1998-01-31 | Add config support for the size of the target address and OF cell. | Andrew Cagney | 1 | -0/+4 |
| 1998-01-26 | Exit status is in r0, not r2 | Michael Meissner | 1 | -0/+4 |
| 1998-01-25 | If DEBUG has 0x20 set, turn traps into batch debugging | Michael Meissner | 1 | -0/+7 |
| 1998-01-23 | First round of d10v ABI changes | Michael Meissner | 2 | -68/+78 |
| 1998-01-22 | * interp.c (UMEM_SEGMENTS): New define, set to 128. | Fred Fish | 2 | -54/+134 |
| 1998-01-20 | * aclocal.m4: Recognize --enable-maintainer-mode. | Doug Evans | 2 | -43/+90 |
| 1997-12-08 | Fix typo, REP_S was refering to REP_E register. | Andrew Cagney | 2 | -1/+5 |
| 1997-12-08 | For "trap", IBT and RIE exceptions, mask all PSW.SM. NB: Stepping | Andrew Cagney | 3 | -87/+165 |
| 1997-12-04 | Regenerate configure files. | Doug Evans | 1 | -0/+4 |
| 1997-12-04 | Add DM (bit 4) to PSW. See 7-1 for more info. | Andrew Cagney | 3 | -0/+10 |
| 1997-12-03 | * d10v_sim.h (SEXT56): Define. | Andrew Cagney | 3 | -54/+48 |
| 1997-12-02 | * interp.c (sim_resume): Call do_2_short with LEFT_FIRST or | Fred Fish | 2 | -26/+36 |
| 1997-12-02 | For "msbu", subtract unsigned product from ACC, | Andrew Cagney | 2 | -4/+9 |
| 1997-12-02 | For "mulxu", store unsigned product in ACC. | Andrew Cagney | 2 | -3/+7 |
| 1997-12-02 | For MACU add unsigned multiply to accumulator. | Andrew Cagney | 2 | -4/+13 |
| 1997-12-02 | For sub2w, compute carry according to negated addition rules. | Andrew Cagney | 2 | -4/+6 |
| 1997-12-01 | Rework sim/common/sim-alu.h to differentiate between direcct | Andrew Cagney | 2 | -11/+40 |
| 1997-11-10 | * simops.c (OP_4201): "rachi". Sign extend bit 40 of ACC. Sign | Andrew Cagney | 1 | -0/+6 |
| 1997-10-25 | Correct name of file given in ChangeLog for change: Pass lma_p and | Andrew Cagney | 1 | -1/+1 |
| 1997-10-24 | Address MSC compiler issues in d10v_sim.h | Andrew Cagney | 1 | -0/+8 |
| 1997-10-22 | Add LMA_P and DO_WRITE arguments to sim/common/sim-load.c:sim_load_file(). | Andrew Cagney | 2 | -2/+29 |
| 1997-10-13 | * simops.c (OP_6A01): Change OP_POSTDEC to OP_POSTINC and move | Fred Fish | 2 | -8/+15 |
| 1997-10-11 | * simops.c (OP_6401): postdecrement on r15 is OK, remove exception. | Fred Fish | 1 | -15/+3 |
| 1997-10-11 | * simops.c (OP_6401): postdecrement on r15 is OK, remove exception. | Fred Fish | 1 | -0/+9 |
| 1997-09-27 | * d10v_sim.h (INC_ADDR): Align MOD_E to increment before testing | Fred Fish | 1 | -0/+2 |
| 1997-09-27 | * interp.c (pc_addr): Discard upper bit(s) of PC in case | Fred Fish | 1 | -0/+9 |
| 1997-09-23 | Remove need to update <targ>/Makefile.in when adding optional options | Andrew Cagney | 2 | -39/+125 |
