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authorFred Fish <fnf@specifix.com>1997-10-13 18:26:52 +0000
committerFred Fish <fnf@specifix.com>1997-10-13 18:26:52 +0000
commit1155e06e3fa4e1e25c3e0aac9edfbb564e6c5428 (patch)
tree81edcf412fc0a3f4cabf011fdf3e2293bf38ae90 /sim/d10v
parentb83093ff7953a93ddccb23ac8266392cd59b7d72 (diff)
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* simops.c (OP_6A01): Change OP_POSTDEC to OP_POSTINC and move
exception generation code to OP_6E01. (OP_6E01): Change OP_POSTINC to OP_POSTDEC and insert exception generation code. PR 13550
Diffstat (limited to 'sim/d10v')
-rw-r--r--sim/d10v/ChangeLog7
-rw-r--r--sim/d10v/simops.c16
2 files changed, 15 insertions, 8 deletions
diff --git a/sim/d10v/ChangeLog b/sim/d10v/ChangeLog
index 409b05f..3ee29c9 100644
--- a/sim/d10v/ChangeLog
+++ b/sim/d10v/ChangeLog
@@ -1,3 +1,10 @@
+Mon Oct 13 10:55:07 1997 Fred Fish <cygnus.com>
+
+ * simops.c (OP_6A01): Change OP_POSTDEC to OP_POSTINC and move
+ exception generation code to OP_6E01.
+ (OP_6E01): Change OP_POSTINC to OP_POSTDEC and insert exception
+ generation code.
+
Sat Oct 11 09:02:08 1997 Fred Fish <fnf@cygnus.com>
* simops.c (OP_6401): postdecrement on r15 is OK, remove exception.
diff --git a/sim/d10v/simops.c b/sim/d10v/simops.c
index ad77e05..df0f826 100644
--- a/sim/d10v/simops.c
+++ b/sim/d10v/simops.c
@@ -2360,13 +2360,7 @@ OP_6E1F ()
void
OP_6A01 ()
{
- trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
- if ( OP[1] == 15 )
- {
- (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
- State.exception = SIGILL;
- return;
- }
+ trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
SW (State.regs[OP[1]], State.regs[OP[0]]);
SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
INC_ADDR (State.regs[OP[1]],4);
@@ -2377,7 +2371,13 @@ OP_6A01 ()
void
OP_6E01 ()
{
- trace_input ("st2w", OP_DREG, OP_POSTINC, OP_VOID);
+ trace_input ("st2w", OP_DREG, OP_POSTDEC, OP_VOID);
+ if ( OP[1] == 15 )
+ {
+ (*d10v_callback->printf_filtered) (d10v_callback, "ERROR: cannot post-decrement register r15 (SP).\n");
+ State.exception = SIGILL;
+ return;
+ }
SW (State.regs[OP[1]], State.regs[OP[0]]);
SW (State.regs[OP[1]]+2, State.regs[OP[0]+1]);
INC_ADDR (State.regs[OP[1]],-4);