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AgeCommit message (Expand)AuthorFilesLines
2024-11-23[sim] Run spellcheck.sh in sim (part 2)Tom de Vries1-1/+1
2024-01-12Update copyright year range in header of all files managed by GDBAndrew Burgess2-2/+2
2024-01-08sim: build: clean more generated outputsMike Frysinger1-0/+1
2023-12-07sim: d10v: fix -Wunused-but-set-variable warningsMike Frysinger1-2/+2
2023-01-18sim: info: convert verbose field to a boolMike Frysinger1-1/+1
2023-01-16sim: formally assume unistd.h always exists (via gnulib)Mike Frysinger1-2/+0
2023-01-15sim: modules.c: fix generation after recent refactorsMike Frysinger1-0/+3
2023-01-14sim: common: move modules.c to source trackingMike Frysinger1-1/+2
2023-01-14sim: build: drop most recursive build depsMike Frysinger1-2/+1
2023-01-14sim: common: move libcommon.a objects to sourcesMike Frysinger1-2/+2
2023-01-11sim: build: drop subdir Makefile.in filesMike Frysinger1-19/+0
2023-01-10sim: move arch-specific file compilation of common/ files to top-levelMike Frysinger1-2/+2
2023-01-10sim: d10v: move arch-specific file compilation to top-levelMike Frysinger1-3/+0
2023-01-10sim: build: drop support for creating libsim.a in subdirsMike Frysinger1-3/+0
2023-01-10sim: d10v: move libsim.a creation to top-levelMike Frysinger2-7/+22
2023-01-10sim: modules: trigger generation from top-levelMike Frysinger1-0/+1
2023-01-02sim: build: move generated headers to built sourcesMike Frysinger1-1/+2
2023-01-01Update copyright year range in header of all files managed by GDBJoel Brobecker3-3/+3
2022-12-25sim: cpu: change default init to handle all cpusMike Frysinger1-1/+1
2022-12-23sim: d10v: move arch-specific settings to internal headerMike Frysinger6-4/+14
2022-12-22sim: move bfd.h include out of sim-main.hMike Frysinger2-1/+2
2022-12-22sim: cr16/d10v/mcore/moxie: clean up unused word & uword typesMike Frysinger1-4/+0
2022-12-22sim: switch sim_{read,write} APIs to 64-bit all the time [PR sim/7504]Mike Frysinger1-6/+6
2022-12-21sim: enable common sim_cpu usage everywhereMike Frysinger1-2/+0
2022-12-20sim: sim_cpu: invert sim_cpu storageMike Frysinger1-5/+2
2022-12-20sim: move register headers into sim/ namespace [PR sim/29869]Mike Frysinger1-1/+1
2022-11-05sim: run: move linking into top-levelMike Frysinger1-0/+8
2022-11-04sim: build: remove various obsolete generation dep variablesMike Frysinger1-5/+0
2022-11-02sim: common: change sim_{fetch,store}_register helpers to use void* buffersMike Frysinger1-4/+4
2022-10-31sim: reg: constify store helperMike Frysinger1-2/+2
2022-10-31sim: constify various integer readersMike Frysinger2-6/+6
2022-10-31sim: common: change sim_read & sim_write to use void* buffersMike Frysinger1-2/+2
2022-08-06Don't use BFD_VMA_FMT in gdb and simAlan Modra1-2/+2
2022-01-06sim: d10v: migrate to standard uintXX_t typesMike Frysinger4-273/+265
2022-01-01Automatic Copyright Year update after running gdb/copyright.pyJoel Brobecker3-3/+3
2021-12-09sim: use ## for automake commentsMike Frysinger1-18/+18
2021-11-28sim: d10v: switch to new target-newlib-syscallMike Frysinger3-36/+26
2021-11-15sim: split program path out of argv vectorMike Frysinger1-4/+1
2021-11-02sim: hoist gencode & opc2c build rules up to common buildsMike Frysinger2-19/+47
2021-11-01sim: d10v: clean up pointer castsMike Frysinger1-6/+6
2021-10-31sim: tighten up gencode outputMike Frysinger1-5/+5
2021-08-17sim: rename ChangeLog files to ChangeLog-2021Mike Frysinger1-0/+0
2021-06-22sim: drop configure scripts for simple portsMike Frysinger4-2893/+6
2021-06-21sim: unify hardware settingsMike Frysinger3-54/+5
2021-06-21sim: hw: rework configure option & device selectionMike Frysinger2-38/+30
2021-06-20sim: delete SIM_AC_COMMON macroMike Frysinger4-5/+5
2021-06-20sim: unify general maintainer settingsMike Frysinger2-124/+0
2021-06-20sim: move sim-inline to the common codeMike Frysinger3-36/+5
2021-06-19sim: unify gettext/intl probing logicMike Frysinger2-85/+0
2021-06-19sim: unify toolchain dependency logicMike Frysinger2-1109/+1
generated by cgit v1.1 at 2024-12-23 12:42:36 +0000