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2019-01-01Update copyright year range in all GDB files.Joel Brobecker1-1/+1
2018-01-02Update copyright year range in all GDB filesJoel Brobecker1-1/+1
2017-01-01update copyright year range in GDB filesJoel Brobecker1-1/+1
2016-01-04sim: unify min/max macrosMike Frysinger1-1/+1
2016-01-01GDB copyright headers update after running GDB's copyright.py script.Joel Brobecker1-1/+1
2015-12-26sim: bfin: avoid stack error under asanMike Frysinger1-1/+1
2015-10-11sim: bfin: handle negative left saturated shifts as ashifts [BZ #18407]Mike Frysinger1-1/+5
2015-06-12sim: trace: add common macros for logging infoMike Frysinger1-10/+10
2015-04-24Fix typos in sim sources exposed by static analysis.Nick Clifton1-1/+1
2015-03-14sim: bfin: fix signed warningMike Frysinger1-1/+1
2015-01-01Update year range in copyright notice of all files owned by the GDB project.Joel Brobecker1-1/+1
2014-01-01Update Copyright year range in all files maintained by GDB.Joel Brobecker1-1/+1
2013-06-24sim: bfin: note missing parallel handling of SEARCHMike Frysinger1-0/+13
2013-06-24sim: bfin: handle invalid HLs encoding in dsp shift insnsMike Frysinger1-5/+9
2013-06-19sim: bfin: stricter insn decodingMike Frysinger1-50/+81
2013-01-01Update years in copyright notice for the GDB files.Joel Brobecker1-1/+1
2012-04-09sim: bfin: fix ASTAT issues in immediate shiftsMike Frysinger1-17/+58
2012-04-09sim: bfin: fix ASTAT/correctness issues with arithmetic shiftsMike Frysinger1-10/+60
2012-04-09sim: bfin: more parallel insn checksMike Frysinger1-18/+66
2012-04-09sim: bfin: keep track of the exact position of parallel insnsMike Frysinger1-44/+49
2012-04-08sim: bfin: drop excess space in negation insnMike Frysinger1-1/+1
2012-04-01sim: bfin: throw VEC_ILGAL_I with 32bit insn in group1/group2 slotsMike Frysinger1-0/+3
2012-04-01sim: bfin: simplify field width processing and fix build warningsMike Frysinger1-10/+1
2012-03-19sim: bfin: fix corner case Logical shift issuesMike Frysinger1-45/+53
2012-01-04Copyright year update in most files of the GDB Project.Joel Brobecker1-1/+1
2011-09-29sim: bfin: use store buffer for VIT_MAX insnsMike Frysinger1-2/+2
2011-06-18sim: bfin: set ASTAT AV/AVS when shifting accumulators overflowMike Frysinger1-0/+6
2011-06-18sim: bfin: do not touch ASTAT[V] when shifting accumulatorsMike Frysinger1-3/+4
2011-06-18sim: bfin: do not extend accumulator in LSHIFT insnsMike Frysinger1-1/+1
2011-06-18sim: bfin: tweak saturation handling with TFU/FU modes and MM bitMike Frysinger1-14/+30
2011-06-18sim: bfin: handle large shift values with accumulator shift insnsMike Frysinger1-2/+8
2011-06-18sim: bfin: handle odd shift values with shift insnsMike Frysinger1-7/+29
2011-06-18sim: bfin: fix M_IH saturation sizeMike Frysinger1-12/+1
2011-06-18sim: bfin: handle V/VS saturation in dsp mac insnsMike Frysinger1-25/+48
2011-06-18sim: bfin: handle the MM flag in M_IU/M_TFU modes with dsp insnsMike Frysinger1-0/+4
2011-06-18sim: bfin: fix sign extension in dsp insns with MM flagMike Frysinger1-8/+3
2011-06-18sim: bfin: fix dsp insns IH saturation/rounding behaviorMike Frysinger1-1/+11
2011-06-18sim: bfin: fix accumulator edge case saturationMike Frysinger1-2/+2
2011-05-14sim: bfin: allow pushing of SPMike Frysinger1-2/+1
2011-04-16sim: bfin: use store buffer with more 32bit insnsMike Frysinger1-23/+29
2011-04-15sim: bfin: handle implicit DISALGNEXCPT with video insnsMike Frysinger1-0/+24
2011-03-29sim: bfin: fix sign extension with 16bit acc add insnsMike Frysinger1-9/+2
2011-03-27sim: bfin: handle saturation with RND12 sub insnsMike Frysinger1-1/+6
2011-03-26sim: bfin: add missing VS set with add/sub insnsMike Frysinger1-0/+3
2011-03-24sim: bfin: update VIT_MAX behavior to match hardware when Acc.X bits are setMike Frysinger1-2/+2
2011-03-24sim: bfin: always do 16bit sign extension with the SEARCH insnMike Frysinger1-0/+5
2011-03-24sim: bfin: update AV and AC ASTAT bits with acc negationMike Frysinger1-6/+8
2011-03-24sim: bfin: allow byteop[123]p src regs to be the sameMike Frysinger1-9/+0
2011-03-15sim: bfin: handle AZ updates with 16bit adds/subsMike Frysinger1-1/+1
2011-03-15sim: bfin: skip acc/ASTAT updates for movesMike Frysinger1-6/+6
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