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| author | Mike Frysinger <vapier@gentoo.org> | 2011-03-27 04:03:05 +0000 |
|---|---|---|
| committer | Mike Frysinger <vapier@gentoo.org> | 2011-03-27 04:03:05 +0000 |
| commit | 36aef94270988051fc9186dfaf4d1e4493e02086 (patch) | |
| tree | 84f8515b76b0401576cd21294278d266af6c4ad5 /sim/bfin/bfin-sim.c | |
| parent | f65d3d6b99f2399eb80708faea6f5e361244e8de (diff) | |
| download | gdb-36aef94270988051fc9186dfaf4d1e4493e02086.zip gdb-36aef94270988051fc9186dfaf4d1e4493e02086.tar.gz gdb-36aef94270988051fc9186dfaf4d1e4493e02086.tar.bz2 | |
sim: bfin: handle saturation with RND12 sub insns
The current handling of the subtraction insn with the RND12 modifier
works when saturation isn't involved. So add handling for this edge
case to match the hardware.
Signed-off-by: Robin Getz <robin.getz@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'sim/bfin/bfin-sim.c')
| -rw-r--r-- | sim/bfin/bfin-sim.c | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/sim/bfin/bfin-sim.c b/sim/bfin/bfin-sim.c index 7e747ff..1555dc2 100644 --- a/sim/bfin/bfin-sim.c +++ b/sim/bfin/bfin-sim.c @@ -4009,7 +4009,12 @@ decode_dsp32alu_0 (SIM_CPU *cpu, bu16 iw0, bu16 iw1) /* If subtract, just invert and add one. */ if (aop & 0x1) - val1 = ~val1 + 1; + { + if (val1 == 0x80000000) + val1 = 0x7FFFFFFF; + else + val1 = ~val1 + 1; + } /* Get the sign bits, since we need them later. */ sBit1 = !!(val0 & 0x80000000); |