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AgeCommit message (Expand)AuthorFilesLines
2019-11-14x86: drop redundant SYSCALL/SYSRET templatesJan Beulich3-26/+5
2019-11-14x86: fold individual Jump* attributes into a single Jump oneJan Beulich5-14858/+10948
2019-11-14x86: make JumpAbsolute an insn attributeJan Beulich6-26480/+26486
2019-11-14x86: make AnySize an insn attributeJan Beulich5-14486/+14499
2019-11-12RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.Jim Wilson2-60/+66
2019-11-12[binutils][arm] Update the decoding of MVE VMOV, VMVNMihail Ionescu2-6/+18
2019-11-12x86: fold EsSeg into IsStringJan Beulich6-11272/+11287
2019-11-12x86: eliminate ImmExt abuseJan Beulich6-93/+197
2019-11-12x86: introduce operand type "instance"Jan Beulich7-14199/+14252
2019-11-11Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same registerJan Beulich2-2/+7
2019-11-11Arm64: fix build with old glibcJan Beulich2-10/+12
2019-11-08i386: Only check suffix in instruction mnemonicH.J. Lu3-4/+10
2019-11-08x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich7-14560/+14574
2019-11-08x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich7-19174/+19187
2019-11-08x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich7-14001/+14015
2019-11-08x86: convert SReg from bitfield to enumeratorJan Beulich7-13810/+13823
2019-11-08x86: introduce operand type "class"Jan Beulich6-105/+165
2019-11-07[gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson3-49/+61
2019-11-07[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson2-0/+19
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson6-462/+877
2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson2-5/+42
2019-11-07[Patch][binutils][arm] Create a new generic coprocessor array [3/10]Matthew Malcomson2-51/+98
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson6-68/+373
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson2-0/+8
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich7-4080/+4160
2019-11-07x86: adjust register names printed for MONITOR/MWAITJan Beulich2-16/+20
2019-11-07x86/Intel: drop IgnoreSize from operand-less MOVSD/CMPSD againJan Beulich3-4/+11
2019-11-05x86: fold OP_Mwaitx() into OP_Mwait()Jan Beulich2-24/+11
2019-11-05x86: split MONITORX/MWAITX entriesJan Beulich2-2/+21
2019-11-05x86: consolidate disassembler enum naming a littleJan Beulich2-75/+130
2019-11-04Fix potential array overruns when disassembling corrupt v850 binaries.Nick Clifton2-60/+129
2019-10-30Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv4-3/+15
2019-10-30x86: re-do "shorthand" handlingJan Beulich4-219/+214
2019-10-30x86: slightly rearrange struct insn_templateJan Beulich4-3918/+3925
2019-10-30x86: drop stray WJan Beulich5-19/+54
2019-10-29Fix array overrun when disassembling corrupt TIC30 binaries.Nick Clifton2-1/+5
2019-10-29Fix a potential illegal array access in the D30V disassembler.Nick Clifton2-1/+9
2019-10-29Prevent a left shift by a negative value when disassembling IA64 binaries.Nick Clifton2-3/+11
2019-10-29Fix array overruns in the S12Z disassembler.Nick Clifton3-16/+56
2019-10-28Fix potentially illegal shift and assign operation in CSKY disassembler.Nick Clifton2-2/+7
2019-10-28Fix buffer overrun in TIC30 disassembler.Nick Clifton2-7/+27
2019-10-28Stop potential illegal memory access in the NS32K disassembler.Nick Clifton2-1/+17
2019-10-28Prevent an illegal memory access in the xgate disassembler.Nick Clifton2-3/+8
2019-10-25Fix potential undefined behaviour in the RX disassembler.Nick Clifton2-1/+6
2019-10-23Fix typo in RX disassembler error messages.Nick Clifton2-10/+19
2019-10-22Prevent more potential illegal memory accesses in the RX disassembler.Nick Clifton2-16/+41
2019-10-16Fix potential illegal memory access when disassembling corrupt RX binaries.Nick Clifton2-15/+92
2019-10-09Fix the disassembly of the LDS and STS instructions of the AVR architecture.Nick Clifton2-0/+8
2019-10-08S/390: Add support for z15 as CPU name.Andreas Krebbel1-1/+2
2019-10-07x86/Intel: correct MOVSD and CMPSD handlingJan Beulich3-12/+18
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