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AgeCommit message (Expand)AuthorFilesLines
2022-06-22RISC-V: Use single h extension to control hypervisor CSRs and instructions.Nelson Chu1-19/+19
2022-06-15x86: drop print_operand_value()'s "hex" parameterJan Beulich1-55/+16
2022-06-13x86: fix incorrect indirectionJan Beulich1-1/+1
2022-06-13x86: replace global scratch bufferJan Beulich1-126/+97
2022-06-13x86: avoid string copy when swapping Vex.W controlled operandsJan Beulich1-6/+8
2022-06-13x86: shrink prefix related disassembler state fieldsJan Beulich1-27/+28
2022-06-13x86: properly initialize struct instr_info instance(s)Jan Beulich1-257/+235
2022-06-08libopcodes: extend the styling within the i386 disassemblerAndrew Burgess1-137/+286
2022-05-30RISC-V: Add zhinx extension supports.jiawei1-56/+56
2022-05-27opcodes/i386: remove trailing whitespace from insns with zero operandsAndrew Burgess1-5/+22
2022-05-27Remove use of bfd_uint64_t and similarAlan Modra3-4/+4
2022-05-27x86: re-work AVX512 embedded rounding / SAEJan Beulich2-11453/+853
2022-05-27x86/Intel: adjust representation of embedded rounding / SAEJan Beulich1-0/+17
2022-05-27x86/Intel: adjust representation of embedded broadcastJan Beulich1-4/+11
2022-05-25opcodes: introduce BC field; fix iselDmitry Selyutin1-2/+5
2022-05-25ppc: extend opindex to 16 bitsDmitry Selyutin1-6/+6
2022-05-20RISC-V: Update zfinx implement with zicsr.Jia-Wei Chen1-14/+14
2022-05-20RISC-V: Remove RV128-only fmv instructionsTsukasa OI1-2/+0
2022-05-18x86: shrink op_riprelJan Beulich1-18/+12
2022-05-17RISC-V: Added half-precision floating-point v1.0 instructions.Nelson Chu1-0/+65
2022-05-12cgen: increase buffer for hash_insn_listAlan Modra1-5/+5
2022-05-11opcodes cgen: remove use of PTRAlan Modra29-1290/+1284
2022-05-10opcodes: remove use of PTRAlan Modra6-6/+6
2022-05-07Fix multiple ubsan warnings in i386-dis.cAlan Modra1-13/+13
2022-05-05Move TILE-Gx files to TARGET64_LIBOPCODES_CFILESLuis Machado2-6/+6
2022-05-05Don't define ARCH_cris for BFD64Luis Machado1-1/+1
2022-05-05IBM zSystems: mgrk, mg first operand requires register pairAndreas Krebbel2-2/+4
2022-04-30opcodes: don't assume ELF in riscv, csky, rl78, mep disassemblersThomas Hebb4-23/+22
2022-04-27x86: VFPCLASSSH is Evex.LLIGJan Beulich2-3/+2
2022-04-19x86: VCMPSH is Evex.LLIGJan Beulich2-98/+98
2022-04-19x86: drop stray CheckRegSize from VFPCLASSPHJan Beulich2-2/+2
2022-04-19x86: correct and simplify NOP disassemblyJan Beulich1-21/+9
2022-04-07IBM zSystems: Add support for z16 as CPU name.Andreas Krebbel2-1/+7
2022-04-04opcodes/i386: partially implement disassembler style supportAndrew Burgess2-24/+46
2022-04-04opcodes/riscv: implement style support in the disassemblerAndrew Burgess2-72/+122
2022-04-04objdump/opcodes: add syntax highlighting to disassembler outputAndrew Burgess2-1/+17
2022-03-31x86: Remove bfd_arch_l1om and bfd_arch_k1omH.J. Lu3-4/+2
2022-03-31aarch64: Relax check for RNG system registersRichard Sandiford1-1/+1
2022-03-29RISC-V: correct FCVT.Q.L[U]Jan Beulich1-2/+2
2022-03-25libtool.m4: fix the NM="/nm/over/here -B/option/with/path" caseNick Alcock1-7/+13
2022-03-24x86: drop L1OM special case from disassemblerJan Beulich1-6/+2
2022-03-20gas:LoongArch: Fix segment error in compilation due to too long symbol name.liuzhensong1-5/+10
2022-03-20ubsan: loongarch : signed integer shift overflow.liuzhensong1-6/+9
2022-03-18x86: also fold remaining multi-vector-size shift insnsJan Beulich2-375/+67
2022-03-18x86: drop stray CheckRegSize from VEXTRACT{F,I}32X4Jan Beulich2-4/+4
2022-03-18x86: fold certain AVX2 templates into their AVX counterpartsJan Beulich2-2284/+558
2022-03-18RISC-V: Cache management instructionsTsukasa OI1-0/+6
2022-03-18RISC-V: Prefetch hint instructions and operand setTsukasa OI2-0/+7
2022-03-17x86: never set i386_cpu_flags' "unused" fieldJan Beulich3-5/+10
2022-03-17x86: unify CPU flag on/off processingJan Beulich2-22/+11
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