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AgeCommit message (Expand)AuthorFilesLines
2023-08-11x86: pack CPU flags in opcode tableJan Beulich4-31432/+4568
2023-08-11RISC-V: Fix opcode entries of "vmsge{,u}.vx"Tsukasa OI1-4/+4
2023-08-09bpf: use w regs in 32-bit non-fetch atomic pseudo-cDavid Faust1-4/+4
2023-08-07RISC-V: move comment describing rules for riscv_opcodes[]Jan Beulich1-10/+10
2023-08-03cris: sprintf optimisationAlan Modra1-19/+10
2023-08-03cris: sprintf sanitizer null destination pointerAlan Modra1-6/+1
2023-08-03 Fix Wlto-type-mismatch in opcodes/ft32-dis.cTom de Vries1-1/+1
2023-08-02Revert "2.41 Release sources"Sam James26-10922/+13254
2023-08-022.41 Release sourcesbinutils-2_41-releaseNick Clifton26-13254/+10922
2023-07-31bpf: opcodes: fix regression in BPF disassemblerJose E. Marchesi2-1/+7
2023-07-30bpf: include, bfd, opcodes: add EF_BPF_CPUVER ELF header flagsJose E. Marchesi3-21/+36
2023-07-28Fix typo in riscv-dis.c commentTsukasa OI1-1/+1
2023-07-27Support Intel PBNDKBHu, Lin17-6040/+6090
2023-07-27Support Intel SM4Haochen Jiang7-6751/+6825
2023-07-27Support Intel SM3Haochen Jiang7-6974/+7105
2023-07-27Support Intel SHA512Haochen Jiang7-7051/+7206
2023-07-27Support Intel AVX-VNNI-INT16konglin17-5622/+9878
2023-07-26bpf: fix register NEG[32] instructionsJose E. Marchesi2-2/+7
2023-07-26Regen bpf opcodes POTFILEAlan Modra3-7/+2
2023-07-25bpf: Add atomic compare-and-exchange instructionsDavid Faust1-0/+12
2023-07-25bpf: Update atomic instruction pseudo-C syntaxDavid Faust1-16/+16
2023-07-24Updated translations for bfd, gold and opcodesNick Clifton1-372/+341
2023-07-24bpf: gas,include,opcode: add suppor for instructions BSWAP{16,32,64}Jose E. Marchesi2-0/+13
2023-07-24bpf: gas,opcodes: fix pseudoc syntax for MOVS* and LDXS* insnsJose E. Marchesi2-10/+15
2023-07-24bpf: add support for jal/gotol jump instruction with 32-bit targetJose E. Marchesi2-0/+8
2023-07-21bpf: disasemble offsets of value 0 as "+0"David Faust1-2/+2
2023-07-21bpf: opcodes, gas: support for signed load V4 instructionsJose E. Marchesi2-0/+15
2023-07-21bpf: opcodes, gas: support for signed register move V4 instructionsJose E. Marchesi2-0/+17
2023-07-21bpf: add missing bpf-dis.c to opcodes/Makefile.amJose E. Marchesi3-0/+8
2023-07-21DesCGENization of the BPF binutils portJose E. Marchesi12-6380/+680
2023-07-21x86: adjust disassembly of insns operating on selector valuesJan Beulich1-6/+6
2023-07-21x86: simplify disassembly of LAR/LSLJan Beulich1-14/+2
2023-07-19Updated Romainian translation for the opcodes directoryNick Clifton1-374/+344
2023-07-18RISC-V: Supports Zcb extension.Jiawei2-0/+42
2023-07-14Fix loongarch build with gcc-4.5Alan Modra1-1/+1
2023-07-11x86: simplify table-referencing macrosJan Beulich1-17/+15
2023-07-11x86: convert 0FXOP to just XOP in enumerator namesJan Beulich1-304/+304
2023-07-11x86: misc further register-only insns don't need to go through mod_table[]Jan Beulich4-163/+77
2023-07-11x86: various operations on mask registers can avoid going through mod_table[]Jan Beulich4-296/+176
2023-07-11x86: slightly rework handling of some register-only insnsJan Beulich2-62/+53
2023-07-11x86: SIMD shift-by-immediate don't need to go through mod_table[]Jan Beulich1-54/+18
2023-07-11x86: misc further memory-only insns don't need to go through mod_table[]Jan Beulich6-315/+124
2023-07-11x86: {,V}MOVNT* don't need to go through mod_table[]Jan Beulich3-64/+18
2023-07-11x86: fold legacy/VEX {,V}MOV{H,L}* entriesJan Beulich2-68/+34
2023-07-11x86: fold certain legacy/VEX table entriesJan Beulich2-305/+109
2023-07-04x86: optimize 128-bit VPBROADCASTQ to VPUNPCKLQDQJan Beulich2-3/+3
2023-07-04x86: optimize pre-AVX512 {,V}PCMPGT* with identical sourcesJan Beulich2-21/+21
2023-07-04x86: optimize pre-AVX512 {,V}PCMPEQQ with identical sourcesJan Beulich2-5/+5
2023-07-04x86: flag bad EVEX masking for miscellaneous insnsJan Beulich6-44/+51
2023-07-04x86: flag EVEX masking when destination is GPR(-like)Jan Beulich1-1/+16
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