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2024-01-12aarch64: Remove unused codeAndrew Carlotti1-34/+0
Most of this code became redundant in my previous commits, but ARMV8_6A_SVE was already dead when it was first added.
2024-01-12aarch64: Make FEAT_ASMv8p2 instruction aliases always availableAndrew Carlotti1-2/+2
There's no reason to disallow the aliases when the aliased instructions are always available. The new behaviour matches existing LLVM behaviour.
2024-01-12aarch64: Add +xs flag for existing instructionsAndrew Carlotti2-2/+7
Additionally, change FEAT_XS tlbi variants to be gated on "+xs" instead of "+d128". This is an incremental improvement; there are still some FEAT_XS tlbi variants that are gated incorrectly or missing entirely.
2024-01-12aarch64: Add +wfxt flag for existing instructionsAndrew Carlotti1-2/+7
2024-01-12aarch64: Add +rcpc2 flag for existing instructionsAndrew Carlotti1-13/+18
2024-01-12aarch64: Add +jscvt flag for existing fjcvtzs instructionAndrew Carlotti1-1/+6
2024-01-11LoongArch: Discard extra spaces in objdump outputLulu Cai1-1/+6
Due to the formatted output of objdump, some instructions that do not require output operands (such as nop/ret) will have extra spaces added after them. Determine whether to output operands through the format of opcodes. When opc->format is an empty string, no extra spaces are output.
2024-01-10gas: aarch64: Add system registers for Debug and PMU extensionsSaurabh Jha1-0/+41
This patch adds support for the new AArch64 system registers that are part of the following extensions: * FEAT_DEBUGv8p9 * FEAT_PMUv3p9 * FEAT_PMUv3_SS * FEAT_PMUv3_ICNTR * FEAT_SEBEP
2024-01-09x86: add missing APX logic to cpu_flags_match()Jan Beulich1-1/+7
As already indicated during review, we can't get away without certain adjustments here: Without these, respective {evex}-prefixed insns are assembled to APX encodings even when APX_F is turned off. While there also extend the respective comment in the opcode table, to explain why this construct is used.
2024-01-09aarch64: ADD FEAT_THE RCWCAS instructions.Srinath Parvathaneni2-139/+961
This patch adds support for FEAT_THE doubleword and quadword instructions. doubleword insturctions are enabled by "+the" flag whereas quadword instructions are enabled on passing both "+the and +d128" flags. Support for following sets of instructions is added in this patch. Read check write compare and swap doubleword: (rcwcas, rcwcasa, rcwcasal, rcwcasl) Read check write compare and swap quadword: (rcwcasp,rcwcaspa, rcwcaspal, rcwcaspl) Read check write software compare and swap doubleword: (rcwscas, rcwscasa, rcwscasal, rcwscasl) Read check write software compare and swap quadword: (rcwscasp, rcwscaspa, rcwscaspal, rcwscaspl) Read check write atomic bit clear on doubleword: (rcwclr, rcwclra, rcwclral, rcwclrl) Read check write atomic bit clear on quadword: (rcwclrp, rcwclrpa, rcwclrpal, rcwclrpl) Read check write software atomic bit clear on doubleword: (rcwsclr, rcwsclra, rcwsclral, rcwsclrl) Read check write software atomic bit clear on quadword: (rcwsclrp,rcwsclrpa, rcwsclrpal,rcwsclrpl) Read check write atomic bit set on doubleword: (rcwset,rcwseta, rcwsetal,rcwsetl) Read check write atomic bit set on quadword: (rcwsetp,rcwsetpa,rcwsetpal,rcwsetpl) Read check write software atomic bit set on doubleword: (rcwsset,rcwsseta,rcwssetal,rcwssetl) Read check write software atomic bit set on quadword: (rcwssetp,rcwssetpa,rcwssetpal,rcwssetpl) Read check write swap doubleword: (rcwswp,rcwswpa,rcwswpal,rcwswpl) Read check write swap quadword: (rcwswpp,rcwswppa, rcwswppal,rcwswppl) Read check write software swap doubleword: (rcwsswp,rcwsswpa,rcwsswpal,rcwsswpl) Read check write software swap quadword: (rcwsswpp,rcwsswppa,rcwsswppal,rcwsswppl)
2024-01-09aarch64: Regenerate aarch64-*-2.c filesVictor Do Nascimento3-2407/+2454
2024-01-09aarch64: Add support for 128-bit system register mrrs and msrr insnsVictor Do Nascimento3-1/+12
With the addition of 128-bit system registers to the Arm architecture starting with Armv9.4-a, a mechanism for manipulating their contents is introduced with the `msrr' and `mrrs' instruction pair. These move values from one such 128-bit system register into a pair of contiguous general-purpose registers and vice-versa, as for example: msrr ttlb0_el1, x0, x1 mrrs x0, x1, ttlb0_el1 This patch adds the necessary support for these instructions, adding checks for system-register width by defining a new operand type in the form of `AARCH64_OPND_SYSREG128' and the `aarch64_sys_reg_128bit_p' predicate, responsible for checking whether the requested system register table entry is marked as implemented in the 128-bit mode via the F_REG_128 flag.
2024-01-09aarch64: Add xs variants of tlbip operandsVictor Do Nascimento2-0/+125
The 2020 Architecture Extensions to the Arm A-profile architecture added FEAT_XS, the XS attribute feature, giving cores the ability to identify devices which can be subject to long response delays. TLB invalidate (TLBI) operations and barriers can also be annotated with this attribute[1]. With the introduction of the 128-bit translation tables with the Armv8.9-a/Armv9.4-a Translation Hardening Extension, a series of new TLB invalidate operations are introduced which make use of this extension. These are added to aarch64_sys_regs_tlbi[] for use with the `tlbip' insn. [1] https://community.arm.com/arm-community-blogs/b/architectures-and-processors-blog/posts/arm-a-profile-architecture-developments-2020
2024-01-09aarch64: Implement TLBIP 128-bit instructionVictor Do Nascimento1-0/+3
The addition of 128-bit page table descriptors and, with it, the addition of 128-bit system registers for these means that special "invalidate translation table entry" instructions are needed to cope with the new 128-bit model. This is introduced with the `tlbpi' instruction, implemented here.
2024-01-09aarch64: Create QL_SRC_X2 and QL_DEST_X2 qualifier macrosVictor Do Nascimento1-0/+12
Some 128-bit system operations (mrrs, msrr, tlbip, and sysp) take two qualified operands and one of unqualified type (e.g. system register name, tlbip operation). This creates the need for adequate qualifiers to handle this. This patch therefore introduces the `QL_SRC_X2' and `QL_DST_X2' qualifier specifiers, which expand to `QLF3(NIL,X,X)' and `QLF3(X,X,NIL)', respectively.
2024-01-09aarch64: Apply narrowing of allowed immediate values for SYSPVictor Do Nascimento1-1/+1
While CRn and CRm fields in the SYSP instruction are 4-bit wide and are thus able to accommodate values in the range 0-15, the specifications for the SYSP instructions limit their ranges to 8-9 for CRm and 0-7 in the case of CRn. This led to the need to signal in some way to the operand parser that a given operand is under special restrictions regarding its use. This is done via the new `F_OPD_NARROW' flag, indicating a narrowing in the range of operand values for fields in the instruction tagged with the flag. The flag is then used in `parse_operands' when the instruction is assembled, but needs not be taken into consideration during disassembly.
2024-01-09aarch64: Add support for the SYSP 128-bit system instructionVictor Do Nascimento3-3/+11
Mirroring the use of the `sys' - System Instruction assembly instruction, this implements its 128-bit counterpart, `sysp'. This optionally takes two contiguous general-purpose registers starting at an even number or, when these are omitted, by default sets both of these to xzr. Syntax: sysp #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>}
2024-01-09aarch64: Add support for xzr register in register pair operandsVictor Do Nascimento3-4/+24
Analysis of the allowed operand values for `sysp' and `tlbip' reveals a significant departure from the allowed behavior for operand register pairs (hitherto labeled AARCH64_OPND_PAIRREG) observed for other insns in this category. For instructions `casp', `mrrs' and `msrr' the register pair must always start at an even index and the second register in the pair is the index + 1. This precludes the use of xzr as the first register, given it corresponds to register number 31. This is different in the case of `sysp' and `tlbip', however. These allow the use of xzr and, where the first operand in the pair is omitted, this is the default value assigned to it. When this operand is assigned xzr, it is expected that the second operand will likewise take on a value of xzr. These two instructions therefore "break" two rules of register pairs: * The first of the two registers is odd-numbered. * The index of the second register is equal to that of the first, and not n+1. To allow for this departure from hitherto standard behavior, we extend the functionality of the assembler by defining an extension of the AARCH64_OPND_PAIRREG, called AARCH64_OPND_PAIRREG_OR_XZR. It is used in defining `sysp' and `tlbip' and allows `operand_general_constraint_met_p' to allow the pair to both take on the value of xzr.
2024-01-09aarch64: Expand maximum number of operands from 5 to 6Victor Do Nascimento1-0/+2
Given the introduction of the new Armv9.4-a `sysp' insn using the following syntax: sysp #<op1>, <Cn>, <Cm>, #<op2>{, <Xt1>, <Xt2>} and by extension the need to encode 6 assembly operands, extend Binutils to handle instructions taking 6 operands, up from a previous maximum of 5.
2024-01-09aarch64: Add +d128 architectural feature supportVictor Do Nascimento1-0/+5
Indicating the presence of the Armv9.4-a features concerning 128-bit Page Table Descriptors, 128-bit System Registers and Instructions, the "+d128" architectural extension flag is added to the list of possible -march options in Binutils, together with the necessary macro for encoding d128 instructions.
2024-01-08aarch64: Add ite feature system registers.srinath1-0/+4
This patch adds ite feature (FEAT_ITE) system registers, trcitecr_el1, trcitecr_el12, trcitecr_el2 and trciteedcr.
2024-01-07i386: Correct adcx suffix in disassemblerH.J. Lu1-4/+13
Since 0x66 is the opcode prefix for adcx, it is wrong to use the 'S' prefix: 'S' => print 'w', 'l' or 'q' if suffix_always is true on adcx. Add 'L' => print 'l' or 'q' if suffix_always is true replace S with L on adcx and adox. gas/ PR binutils/31219 * testsuite/gas/i386/suffix.d: Updated. * testsuite/gas/i386/x86-64-suffix.d: Likewise. * testsuite/gas/i386/suffix.s: Add tests for adcx and adox. * testsuite/gas/i386/x86-64-suffix.s: Likewise. opcodes/ PR binutils/31219 * i386-dis.c: Add the 'L' suffix. (prefix_table): Replace S with L on adcx and adox. (putop): Handle the 'L' suffix.
2024-01-05Add AMD znver5 processor supportTejas Joshi2-0/+12
gas/ * config/tc-i386.c (cpu_arch): Add znver5 ARCH. * doc/c-i386.texi: Add znver5. * testsuite/gas/i386/arch-15.d: New. * testsuite/gas/i386/arch-15.s: Likewise. * testsuite/gas/i386/arch-15-znver5.d: Likewise. * testsuite/gas/i386/i386.exp: Add new znver5 test cases. * testsuite/gas/i386/x86-64.exp: Likewise. * testsuite/gas/i386/x86-64-arch-5.d: Likewise. * testsuite/gas/i386/x86-64-arch-5.s: Likewise. * testsuite/gas/i386/x86-64-arch-5-znver5.d: Likewise. opcodes/ * i386-gen.c (isa_dependencies): Add ZNVER5 dependencies. * i386-init.h: Re-generated.
2024-01-05x86: corrections to CPU attribute/flags splittingJan Beulich1-1/+10
There are a number of issues with 734dfd1cc966 ("x86: pack CPU flags in opcode table"): - the condition when two array slots need writing wasn't correct (with enough new Cpu* added an out of bounds array access would validly have been complained about by the compiler), - table generation didn't take into account CpuAttrUnused and CpuUnused being independent, and hence there not always (not) being an "unused" bitfield member in both structures, - cpu_flags_from_attr() wasn't ready for use on big-endian hosts, - there were two style violations.
2024-01-05RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvliJin Ma2-1/+35
Since the particularity of "th.vsetvli" was not taken into account in the initial support patches for XTheadVector, the program operation failed due to instruction coding errors. According to T-Head SPEC ([1]), the "vsetvl" in the XTheadVector extension consists of SEW, LMUL and EDIV, which is quite different from the "V" extension. Therefore, we cannot simply reuse the processing of vsetvl in V extension. We have set up tens of thousands of test cases to ensure that no further encoding issues are there, and and execute all compiled test files on real HW and make sure they don't trigger SIGILL. Ref: [1] https://github.com/T-head-Semi/thead-extension-spec/releases/download/2.3.0/xthead-2023-11-10-2.3.0.pdf Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * config/tc-riscv.c (validate_riscv_insn): Add handling for th.vsetvli. (my_getThVsetvliExpression): New function. (riscv_ip): Likewise. * testsuite/gas/riscv/x-thead-vector.d: Likewise. * testsuite/gas/riscv/x-thead-vector.s: Likewise. include/ChangeLog: * opcode/riscv.h (OP_MASK_XTHEADVLMUL): New macro. (OP_SH_XTHEADVLMUL): Likewise. (OP_MASK_XTHEADVSEW): Likewise. (OP_SH_XTHEADVSEW): Likewise. (OP_MASK_XTHEADVEDIV): Likewise. (OP_SH_XTHEADVEDIV): Likewise. (OP_MASK_XTHEADVTYPE_RES): Likewise. (OP_SH_XTHEADVTYPE_RES): Likewise. opcodes/ChangeLog: * riscv-dis.c (print_insn_args): Likewise. * riscv-opc.c: Likewise.
2024-01-04Update year range in copyright notice of binutils filesAlan Modra275-336/+340
Adds two new external authors to etc/update-copyright.py to cover bfd/ax_tls.m4, and adds gprofng to dirs handled automatically, then updates copyright messages as follows: 1) Update cgen/utils.scm emitted copyrights. 2) Run "etc/update-copyright.py --this-year" with an extra external author I haven't committed, 'Kalray SA.', to cover gas testsuite files (which should have their copyright message removed). 3) Build with --enable-maintainer-mode --enable-cgen-maint=yes. 4) Check out */po/*.pot which we don't update frequently.
2024-01-04LoongArch: Fix some macro that cannot be expanded properlyLulu Cai1-12/+12
Suppose we want to use la.got to generate 32 pcrel and 32 abs instruction sequences respectively. According to the existing conditions, to generate 32 pcrel sequences use -mabi=ilp32*, and to generate 32 abs use -mabi=ilp32* and -mla-global-with-abs. Due to the fact that the conditions for generating 32 abs also satisfy 32 pcrel, using -mabi=ilp32* and -mla-global-with-abs will result in only generating instruction sequences of 32 pcrel. By modifying the conditions for macro expansion and adjusting the matching order of macro instructions, it is ensured that the correct sequence of instructions can be generated.
2023-12-30LoongArch: Commas inside double quotesAlan Modra1-1/+5
This adds an extra feature: Commas inside double quotes are not an arg delimiter, and thus can be part of the arg. * loongarch-coder.c (loongarch_split_args_by_comma): Commas inside quotes are not arg delimiters.
2023-12-29LoongArch: opcodes: Add support for tls le relax.changjiachen1-0/+1
Add new opcode for tls le relax. opcode/ChangeLog: * loongarch-opc.c: Add new loongarch opcode.
2023-12-29RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extensionJin Ma1-0/+5
In order to make it easier to complete the compiler's support for the XTheadVector extension and to be as compatible as possible with the programming model of the 'V' extension ([1]), we consider adding a few pseudo instructions ([2]). th.vmmv.m vd,vs => th.vmand.mm vd,vs,vs th.vneg.v vd,vs => th.vrsub.vx vd,vs,x0 th.vncvt.x.x.v vd,vs,vm => th.vnsrl.vx vd,vs,x0,vm th.vfneg.v vd,vs => th.vfsgnjn.vv vd,vs,vs th.vfabs.v vd,vs => th.vfsgnjx.vv vd,vs,vs Ref: [1] https://gcc.gnu.org/pipermail/gcc-patches/2023-December/641302.html [2] https://github.com/T-head-Semi/thead-extension-spec/pull/40 Co-developed-by: Lifang Xia <lifang_xia@linux.alibaba.com> Co-developed-by: Christoph Müllner <christoph.muellner@vrull.eu> gas/ChangeLog: * testsuite/gas/riscv/x-thead-vector.d: Add tests for new pseudoinstructions. * testsuite/gas/riscv/x-thead-vector.s: Likewise. opcodes/ChangeLog: * riscv-opc.c: Add new pseudoinstructions.
2023-12-28Support APX JMPABS for disassemblerHu, Lin11-2/+35
gas/ChangeLog: * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs.d: Ditto. * testsuite/gas/i386/x86-64-apx-jmpabs.s: Ditto. opcodes/ChangeLog: * i386-dis.c (JMPABS_Fixup): New Fixup function to disassemble jmpabs. (print_insn): Add #UD exception for jmpabs. (dis386): Modify a1 unit for support jmpabs. * i386-mnem.h: Regenerated. * i386-opc.tbl: New insns. * i386-tbl.h: Regenerated.
2023-12-28Support APX pushp/poppCui, Lili5-1061/+1101
gas/ChangeLog: * config/tc-i386.c (process_operands): Handle "PUSHP/POPP requires rex2.w == 1." * testsuite/gas/i386/x86-64.exp: Add new test for PUSHP/POPP. * testsuite/gas/i386/x86-64-apx-pushp-popp-intel.d: New test. * testsuite/gas/i386/x86-64-apx-pushp-popp-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp-inval.s: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp.d: Ditto. * testsuite/gas/i386/x86-64-apx-pushp-popp.s: Ditto. opcodes/ChangeLog: * i386-dis.c (putop): print pushp and popp. * i386-opc.tbl: Added new insns. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-tbl.h: Regenerated.
2023-12-28Support APX Push2/Pop2Mo, Zewei7-1960/+2064
PPX functionality for PUSH/POP is not implemented in this patch and will be implemented separately. gas/ChangeLog: 2023-12-28 Zewei Mo <zewei.mo@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> * config/tc-i386.c: (enum i386_error): New unsupported_rsp_register and invalid_src_register_set. (md_assemble): Add handler for unsupported_rsp_register and invalid_src_register_set. (check_APX_operands): Add invalid check for push2/pop2. (match_template): Handle check_APX_operands. * testsuite/gas/i386/i386.exp: Add apx-push2pop2 tests. * testsuite/gas/i386/x86-64.exp: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2.d: New test. * testsuite/gas/i386/x86-64-apx-push2pop2.s: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-intel.d: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.l: Ditto. * testsuite/gas/i386/x86-64-apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.s: Ditto. * testsuite/gas/i386/apx-push2pop2-inval.d: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d: Added bad testcases for POP2. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s: Ditto. opcodes/ChangeLog: * i386-dis-evex-reg.h: Add REG_EVEX_MAP4_8F. * i386-dis-evex-w.h: Add EVEX_W_MAP4_8F_R_0 and EVEX_W_MAP4_FF_R_6 * i386-dis-evex.h: Add REG_EVEX_MAP4_8F. * i386-dis.c (PUSH2_POP2_Fixup): Add special handling for PUSH2/POP2. (get_valid_dis386): Add handler for vector length and address_mode for APX-Push2/Pop2 insn. (nd): define nd as b for EVEX-promoted instrutions. (OP_VEX): Add handler of 64-bit vvvv register for APX-Push2/Pop2 insn. * i386-gen.c: Add Push2Pop2 bitfield. * i386-opc.h: Regenerated. * i386-opc.tbl: Regenerated.
2023-12-28Support APX NDDkonglin16-413/+1650
opcodes/ChangeLog: * opcodes/i386-dis-evex-reg.h: Handle for REG_EVEX_MAP4_80, REG_EVEX_MAP4_81, REG_EVEX_MAP4_83, REG_EVEX_MAP4_F6, REG_EVEX_MAP4_F7, REG_EVEX_MAP4_FE, REG_EVEX_MAP4_FF. * opcodes/i386-dis-evex.h: Add NDD insn. * opcodes/i386-dis.c (nd): New define. (VexGb): Ditto. (VexGv): Ditto. (get_valid_dis386): Change for NDD decode. (print_insn): Ditto. (putop): Ditto. (intel_operand_size): Ditto. (OP_E_memory): Ditto. (OP_VEX): Ditto. * opcodes/i386-opc.h (VexVVVV_DST): New. * opcodes/i386-opc.tbl: Add APX NDD instructions and adjust VexVVVV. * opcodes/i386-tbl.h: Regenerated. gas/ChangeLog: * gas/config/tc-i386.c (operand_size_match): Support APX NDD that the number of operands is 3. (build_apx_evex_prefix): Change for ndd encode. (process_operands): Ditto. (build_modrm_byte): Ditto. (match_template): Support swap the first two operands for APX NDD. * testsuite/gas/i386/x86-64.exp: Add x86-64-apx-ndd. * testsuite/gas/i386/x86-64-apx-ndd.d: New test. * testsuite/gas/i386/x86-64-apx-ndd.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.d : Ditto. * testsuite/gas/i386/x86-64-apx-evex-promoted-bad.s : Ditto.
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili8-4182/+4772
This patch adds non-ND, non-NF forms of EVEX promotion insn. EVEX extension of legacy instructions: All promoted legacy instructions are placed in EVEX map 4, which is currently reserved. EVEX extension of EVEX instructions: All existing EVEX instructions are extended by APX using the extended EVEX prefix, so that they can access all 32 GPRs. EVEX extension of VEX instructions: Promoting a VEX instruction into the EVEX space does not change the map id, the opcode, or the operand encoding of the VEX instruction. Note: The promoted versions of MOVBE will be extended to include the “MOVBE reg1, reg2”. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (struct _i386_insn): Add has_egpr. (need_evex_encoding): Adjusted for apx. (cpu_flags_match): Ditto. (install_template): Handled APX combines. (is_apx_evex_encoding): Test apx evex encoding. (build_apx_evex_prefix): Enabe APX evex prefix. (md_assemble): Handle apx with evex encoding. (process_suffix): Handle apx map4 prefix. (check_register): Assign i.vec_encoding for APX evex instructions. * testsuite/gas/i386/x86-64-evex.d: Adjust test cases. * testsuite/gas/i386/x86-64.exp: Adjust x86-64-inval-movbe. opcodes/ChangeLog: * i386-dis-evex-len.h: Handle EVEX_LEN_0F38F2, EVEX_LEN_0F38F3. * i386-dis-evex-prefix.h: Handle PREFIX_EVEX_0F38F2_L_0, PREFIX_EVEX_0F38F3_L_0, PREFIX_EVEX_MAP4_D8, PREFIX_EVEX_MAP4_DA, PREFIX_EVEX_MAP4_DB, PREFIX_EVEX_MAP4_DC, PREFIX_EVEX_MAP4_DD, PREFIX_EVEX_MAP4_DE, PREFIX_EVEX_MAP4_DF, PREFIX_EVEX_MAP4_F0, PREFIX_EVEX_MAP4_F1, PREFIX_EVEX_MAP4_F2, PREFIX_EVEX_MAP4_F8. * i386-dis-evex-reg.h: Handle REG_EVEX_0F38F3_L_0_P_0. * i386-dis-evex.h: Add EVEX_MAP4_ for legacy insn promote to apx to use gpr32 * opcodes/i386-dis-evex-x86-64.h: Handle Add X86_64_EVEX_0F90, X86_64_EVEX_0F92, X86_64_EVEX_0F93, X86_64_EVEX_0F38F2, X86_64_EVEX_0F38F3, X86_64_EVEX_0F38F5, X86_64_EVEX_0F38F6, X86_64_EVEX_0F38F7, X86_64_EVEX_0F3AF0, X86_64_EVEX_0F91. * i386-dis.c (struct instr_info): Deleted bool r. (PREFIX_NP_OR_DATA): New. (NO_PREFIX): New. (putop): Ditto. (X86_64_EVEX_FROM_VEX_TABLE): Diito. (get_valid_dis386): Decode insn erex in extend evex prefix. Handle EVEX_MAP4 (print_insn): Handle PREFIX_DATA_AND_NP_ONLY. (print_register): Handle apx instructions decode. (OP_E_memory): Diito. (OP_G): Diito. (OP_XMM): Diito. (DistinctDest_Fixup): Diito. * i386-gen.c (process_i386_opcode_modifier): Add EVEXMAP4. * i386-opc.h (SPACE_EVEXMAP4): Add legacy insn promote to evex. * i386-opc.tbl: Handle some legacy and vex insns don't support gpr32. And add some legacy insn (map2 / 3) promote to evex.
2023-12-28Created an empty EVEX_MAP4_ sub-table for EVEX instructions.Cui, Lili2-0/+292
opcode/ChangeLog: * i386-dis-evex.hi: Added an empty EVEX_MAP4_ sub-table for legacy insn promote to EVEX insn. * opcodes/i386-dis-evex.h: Add EVEX_MAP4.
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili8-11743/+12227
APX uses the REX2 prefix to support EGPR for map0 and map1 of legacy instructions. We added the NoEgpr flag in i386-gen.c for instructions that do not support EGPR. gas/ChangeLog: 2023-12-28 Lingling Kong <lingling.kong@intel.com> H.J. Lu <hongjiu.lu@intel.com> Lili Cui <lili.cui@intel.com> Lin Hu <lin1.hu@intel.com> * config/tc-i386.c (enum i386_error): Add unsupported_EGPR_for_addressing and invalid_pseudo_prefix. (struct _i386_insn): Add rex2 and rex2_encoding for gpr32. (cpu_arch): Add apx_f. (is_cpu): Ditto. (register_number): Handle RegRex2 for gpr32. (is_apx_rex2_encoding): New func. Test rex2 prefix encoding. (build_rex2_prefix): New func. Build legacy insn in opcode 0/1 use gpr32 with rex2 prefix. (establish_rex): Handle rex2 and rex2_encoding. (optimize_encoding): Handel add r16-r31 for registers. (md_assemble): Handle apx encoding. (parse_insn): Handle Prefix_REX2. (check_EgprOperands): New func. Check if Egprs operands are valid for the instruction (match_template): Handle Egpr operands check. (set_rex_rex2): New func. set i.rex and i.rex2. (build_modrm_byte): Ditto. (output_insn): Handle rex2 2-byte prefix output. (check_register): Handle check egpr illegal without target apx, 64-bit mode and with rex_prefix. * doc/c-i386.texi: Document .apx. * testsuite/gas/i386/ilp32/x86-64-opcode-inval-intel.d: D5 valid in 64-bit mode. * testsuite/gas/i386/ilp32/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/rex-bad: Adjust rex testcase. * testsuite/gas/i386/x86-64-opcode-inval-intel.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.d: Ditto. * testsuite/gas/i386/x86-64-opcode-inval.s: Ditto. * testsuite/gas/i386/x86-64-pseudos-bad.l: Add illegal rex2 test. * testsuite/gas/i386/x86-64-pseudos-bad.s: Ditto. * testsuite/gas/i386/x86-64-pseudos.d: Add rex2 test. * testsuite/gas/i386/x86-64-pseudos.s: Ditto. * testsuite/gas/i386/x86-64.exp: Run APX tests. * testsuite/gas/i386/x86-64-apx-egpr-inval.l: New test. * testsuite/gas/i386/x86-64-apx-egpr-inval.s: New test. * testsuite/gas/i386/x86-64-apx-rex2.d: New test. * testsuite/gas/i386/x86-64-apx-rex2.s: New test. include/ChangeLog: * opcode/i386.h (REX2_OPCODE): New. (REX2_M): Ditto. opcodes/ChangeLog: * i386-dis.c (struct instr_info): Add erex for gpr32. Add last_erex_prefix for rex2 prefix. (REX2_M): Extend for gpr32. (PREFIX_REX2): Ditto. (PREFIX_REX2_ILLEGAL): Ditto. (ckprefix): Ditto. (prefix_name): Ditto. (print_insn): Ditto. (print_register): Ditto. (OP_E_memory): Ditto. (OP_REG): Ditto. (OP_EX): Ditto. * i386-gen.c (rex2_disallowed): Some instructions are not allowed rex2 prefix. (process_i386_opcode_modifier): Set NoEgpr for VEX and some special instructions. (output_i386_opcode): Handle if_entry_needs_special_handle. * i386-init.h : Regenerated. * i386-mnem.h : Regenerated. * i386-opc.h (enum i386_cpu): Add CpuAPX_F. (NoEgpr): New. (Prefix_NoOptimize): Ditto. (Prefix_REX2): Ditto. (RegRex2): Ditto. * i386-opc.tbl: Add rex2 prefix. * i386-reg.tbl: Add egprs (r16-r31). * i386-tbl.h: Regenerated.
2023-12-25LoongArch: Add new relocs and macro for TLSDESC.Lulu Cai1-0/+54
The normal DESC instruction sequence is: pcalau12i $a0,%desc_pc_hi20(var) #R_LARCH_TLS_DESC_PC_HI20 addi.d $a0,$a0,%desc_pc_lo12(var) #R_LARCH_TLS_DESC_PC_LO12 ld.d $ra,$a0,%desc_ld(var) #R_LARCH_TLS_DESC_LD jirl $ra,$ra,%desc_call(var) #R_LARCH_TLS_DESC_CALL add.d $a0,$a0,$tp
2023-12-25Re: LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">Alan Modra1-14/+16
This fixes the buffer overflow added in commit 22b78fad28, and a few other problems. * loongarch-coder.c (loongarch_split_args_by_comma): Don't overflow buffer when args == "". Don't remove unbalanced quotes. Don't trim last arg if max number of args exceeded.
2023-12-20s390: Add suffix to conditional branch instruction descriptionsJens Remus1-34/+44
Suffix the instruction description of conditional branch extended mnemonics with their condition (e.g. "on A high"). This complements the optional printing of instruction descriptions as comments in the disassembly. Due to the added text the maximum description length is increased from 80 to 128 characters (including the trailing '\0' character). opcodes/ * s390-mkopc.c: Add suffix to conditional branch extended mnemonic instruction descriptions. gas/ * testsuite/gas/s390/zarch-insndesc.s: Add test cases for printing of suffixed instruction description of conditional branch extended mnemonics. * testsuite/gas/s390/zarch-insndesc.d: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-20s390: Optionally print instruction description in disassemblyJens Remus3-39/+55
Print instruction description as comment in disassembly with s390 architecture specific option "insndesc": - For objdump it can be enabled with option "-M insndesc" - In gdb it can be enabled with "set disassembler-options insndesc" Since comments are not column aligned the output can enhanced for readability by postprocessing using a filter such as "expand": ... | expand -t 8,16,24,32,40,80 Or when using in combination with objdump option --visualize-jumps: ... | expand | sed -e 's/ *#/\t#/' | expand -t 1,80 Note that the instruction descriptions add about 128 KB to s390-opc.o: s390-opc.o without instruction descriptions: 216368 bytes s390-opc.o with instruction descriptions : 348432 bytes binutils/ * NEWS: Mention new s390-specific disassembler option "insndesc". include/ * opcode/s390.h (struct s390_opcode): Add field to hold instruction description. opcodes/ * s390-mkopc.c: Copy instruction description from s390-opc.txt into generated operation code table s390-opc.tab. * s390-opc.c (s390_opformats): Provide NULL as description in .insn pseudo-mnemonics opcode table. * s390-dis.c: Add s390-specific disassembler option "insndesc" and optionally print the instruction description as comment in the disassembly when it is specified. gas/ * testsuite/gas/s390/s390.exp: Add new test disassembly test case "zarch-insndesc". * testsuite/gas/s390/zarch-insndesc.s: New test case for s390- specific disassembler option "insndesc". * testsuite/gas/s390/zarch-insndesc.d: Likewise. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-20s390: Use safe string functions and length macros in s390-mkopcJens Remus1-25/+52
Use strncpy() and snprintf() instead of strcpy() and strcat(). Define and use macros for string lengths, such as mnemonic, instruction format, and instruction description. This is a mechanical change, although some buffers have increased in length by one character. This has been confirmed by verifying that the generated opcode/s390-opc.tab is unchanged. opcodes/ * s390-mkopc.c: Use strncpy() and strncat(). Suggested-by: Nick Clifton <nickc@redhat.com> Signed-off-by: Jens Remus <jremus@linux.ibm.com> Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-20s390: Enhance error handling in s390-mkopcJens Remus1-14/+35
When the s390-mkopc utility detects an error it prints an error message to strerr and either continues processing or exists with a non-zero return code. If it continues without detecting any further error the final return code was zero, potentially hiding the detected error. Introduce a global variable to hold the final return code and initialize it to EXIT_SUCCESS. Introduce a helper function print_error() that prints an error message to stderr and sets the final return code to EXIT_FAILURE. Use it to print all error messages. Return the final return code at the end of the processing. While at it enhance error messages to state more clearly which mnemonic an error was detected for. Also continue processing for cases where subsequent mnemonics can be processed. opcodes/ * s390-mkopc.c: Enhance error handling. Return EXIT_FAILURE in case of an error, otherwise EXIT_SUCCESS. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-20s390: Provide IBM z16 (arch14) instruction descriptionsJens Remus1-28/+38
Provide descriptions for instructions introduced with commit ba2b480f103 ("IBM Z: Implement instruction set extensions"). This complements commit 69341966def ("IBM zSystems: Add support for z16 as CPU name."). Use instruction names from IBM z/Architecture Principles of Operation [1] as instruction description. [1]: IBM z/Architecture Principles of Operation, SA22-7832-13, IBM z16, https://publibfp.dhe.ibm.com/epubs/pdf/a227832d.pdf opcodes/ * s390-opc.txt: Add descriptions for IBM z16 (arch14) instructions. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-20s390: Align letter case of instruction descriptionsJens Remus1-21/+21
Change the bitwise operations names "and" and "or" to lower case. Change the register name abbreviations "FPR", "GR", and "VR" to upper case. opcodes/ * s390-opc.txt: Align letter case of instruction descriptions. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-20s390: Fix build when using EXEEXT_FOR_BUILDJens Remus2-4/+10
Suffix the s390-mkopc build utility executable file name with EXEEXT_FOR_BUILD. Otherwise it cannot be located when building with EXEEXT_FOR_BUILD. Use pattern used for other architecture build utilities and compile and link s390-mkopc in two steps. While at it also specify the dependencies of s390-mkopc.c. opcodes/ * Makefile.am: Add target to build s390-mkopc.o. Correct target to build s390-mkopc$(EXEEXT_FOR_BUILD). * Makefile.in: Regenerate. Signed-off-by: Jens Remus <jremus@linux.ibm.com> Reviewed-by: Andreas Krebbel <krebbel@linux.ibm.com>
2023-12-19aarch64: Add FEAT_ITE supportAndrea Corallo3-2/+12
This patch add support for FEAT_ITE "Instrumentation Extension" adding the "trcit" instruction. This is enabled by the +ite march flag.
2023-12-19aarch64: Add FEAT_ECBHB supportAndrea Corallo3-1/+7
This patch add support for FEAT_ECBHB "Exploitative control using branch history information" adding the "clrbhb" instruction. AFAIU the same alias was originally added as "clearbhb" before the architecture was finalized (Mandatory v8.9-a/v9.4-a; Optional v8.0-a+/v9.0-a+).
2023-12-19aarch64: Add FEAT_SPECRES2 supportAndrea Corallo4-2074/+2083
This patch add supports for FEAT_SPECRES2 "Enhanced speculation restriction instructions" adding the "cosp" instruction. This is mandatory v8.9-a/v9.4-a and optional v8.0-a+/v9.0-a+. It is enabled by the +predres2 march flag.
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang4-3777/+3762
Since AVX10.1/256 will also allow 64 bit mask register, we will remove the restriction for size of the mask register in AVX10. gas/ChangeLog: * config/tc-i386.c (VSZ128, VSZ256, VSZ512): New. (VEX_check_encoding): Remove opcode_modifier check for vsz. * testsuite/gas/i386/avx10-vsz.l: Remove testcases for mask registers since they are not needed. * testsuite/gas/i386/avx10-vsz.s: Ditto. opcodes/ChangeLog: * i386-gen.c: Remove Vsz. * i386-opc.h: Ditto. * i386-opc.tbl: Remove kvsz. * i386-tbl.h: Regenerated.