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2024-01-12aarch64: Remove unused codeAndrew Carlotti1-34/+0
2024-01-12aarch64: Make FEAT_ASMv8p2 instruction aliases always availableAndrew Carlotti1-2/+2
2024-01-12aarch64: Add +xs flag for existing instructionsAndrew Carlotti2-2/+7
2024-01-12aarch64: Add +wfxt flag for existing instructionsAndrew Carlotti1-2/+7
2024-01-12aarch64: Add +rcpc2 flag for existing instructionsAndrew Carlotti1-13/+18
2024-01-12aarch64: Add +jscvt flag for existing fjcvtzs instructionAndrew Carlotti1-1/+6
2024-01-11LoongArch: Discard extra spaces in objdump outputLulu Cai1-1/+6
2024-01-10gas: aarch64: Add system registers for Debug and PMU extensionsSaurabh Jha1-0/+41
2024-01-09x86: add missing APX logic to cpu_flags_match()Jan Beulich1-1/+7
2024-01-09aarch64: ADD FEAT_THE RCWCAS instructions.Srinath Parvathaneni2-139/+961
2024-01-09aarch64: Regenerate aarch64-*-2.c filesVictor Do Nascimento3-2407/+2454
2024-01-09aarch64: Add support for 128-bit system register mrrs and msrr insnsVictor Do Nascimento3-1/+12
2024-01-09aarch64: Add xs variants of tlbip operandsVictor Do Nascimento2-0/+125
2024-01-09aarch64: Implement TLBIP 128-bit instructionVictor Do Nascimento1-0/+3
2024-01-09aarch64: Create QL_SRC_X2 and QL_DEST_X2 qualifier macrosVictor Do Nascimento1-0/+12
2024-01-09aarch64: Apply narrowing of allowed immediate values for SYSPVictor Do Nascimento1-1/+1
2024-01-09aarch64: Add support for the SYSP 128-bit system instructionVictor Do Nascimento3-3/+11
2024-01-09aarch64: Add support for xzr register in register pair operandsVictor Do Nascimento3-4/+24
2024-01-09aarch64: Expand maximum number of operands from 5 to 6Victor Do Nascimento1-0/+2
2024-01-09aarch64: Add +d128 architectural feature supportVictor Do Nascimento1-0/+5
2024-01-08aarch64: Add ite feature system registers.srinath1-0/+4
2024-01-07i386: Correct adcx suffix in disassemblerH.J. Lu1-4/+13
2024-01-05Add AMD znver5 processor supportTejas Joshi2-0/+12
2024-01-05x86: corrections to CPU attribute/flags splittingJan Beulich1-1/+10
2024-01-05RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvliJin Ma2-1/+35
2024-01-04Update year range in copyright notice of binutils filesAlan Modra275-336/+340
2024-01-04LoongArch: Fix some macro that cannot be expanded properlyLulu Cai1-12/+12
2023-12-30LoongArch: Commas inside double quotesAlan Modra1-1/+5
2023-12-29LoongArch: opcodes: Add support for tls le relax.changjiachen1-0/+1
2023-12-29RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extensionJin Ma1-0/+5
2023-12-28Support APX JMPABS for disassemblerHu, Lin11-2/+35
2023-12-28Support APX pushp/poppCui, Lili5-1061/+1101
2023-12-28Support APX Push2/Pop2Mo, Zewei7-1960/+2064
2023-12-28Support APX NDDkonglin16-413/+1650
2023-12-28Support APX GPR32 with extend evex prefixCui, Lili8-4182/+4772
2023-12-28Created an empty EVEX_MAP4_ sub-table for EVEX instructions.Cui, Lili2-0/+292
2023-12-28Support APX GPR32 with rex2 prefixCui, Lili8-11743/+12227
2023-12-25LoongArch: Add new relocs and macro for TLSDESC.Lulu Cai1-0/+54
2023-12-25Re: LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1">Alan Modra1-14/+16
2023-12-20s390: Add suffix to conditional branch instruction descriptionsJens Remus1-34/+44
2023-12-20s390: Optionally print instruction description in disassemblyJens Remus3-39/+55
2023-12-20s390: Use safe string functions and length macros in s390-mkopcJens Remus1-25/+52
2023-12-20s390: Enhance error handling in s390-mkopcJens Remus1-14/+35
2023-12-20s390: Provide IBM z16 (arch14) instruction descriptionsJens Remus1-28/+38
2023-12-20s390: Align letter case of instruction descriptionsJens Remus1-21/+21
2023-12-20s390: Fix build when using EXEEXT_FOR_BUILDJens Remus2-4/+10
2023-12-19aarch64: Add FEAT_ITE supportAndrea Corallo3-2/+12
2023-12-19aarch64: Add FEAT_ECBHB supportAndrea Corallo3-1/+7
2023-12-19aarch64: Add FEAT_SPECRES2 supportAndrea Corallo4-2074/+2083
2023-12-19x86: Remove the restriction for size of the mask register in AVX10Haochen Jiang4-3777/+3762
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