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| author | Lulu Cai <cailulu@loongson.cn> | 2023-12-27 19:42:01 +0800 |
|---|---|---|
| committer | liuzhensong <liuzhensong@loongson.cn> | 2024-01-04 16:44:12 +0800 |
| commit | 1c729b7cd77ca69f0f41d6a92ccf67348f08e007 (patch) | |
| tree | da6e8cafa9b52c7778888871a3b35fd00a6943b0 /opcodes | |
| parent | 3fc4f11e0bf30abfcf0abe803c38eddc8da9e301 (diff) | |
| download | gdb-1c729b7cd77ca69f0f41d6a92ccf67348f08e007.zip gdb-1c729b7cd77ca69f0f41d6a92ccf67348f08e007.tar.gz gdb-1c729b7cd77ca69f0f41d6a92ccf67348f08e007.tar.bz2 | |
LoongArch: Fix some macro that cannot be expanded properly
Suppose we want to use la.got to generate 32 pcrel and
32 abs instruction sequences respectively. According to
the existing conditions, to generate 32 pcrel sequences
use -mabi=ilp32*, and to generate 32 abs use -mabi=ilp32*
and -mla-global-with-abs.
Due to the fact that the conditions for generating 32 abs
also satisfy 32 pcrel, using -mabi=ilp32* and -mla-global-with-abs
will result in only generating instruction sequences of 32 pcrel.
By modifying the conditions for macro expansion and adjusting
the matching order of macro instructions, it is ensured that
the correct sequence of instructions can be generated.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/loongarch-opc.c | 24 |
1 files changed, 12 insertions, 12 deletions
diff --git a/opcodes/loongarch-opc.c b/opcodes/loongarch-opc.c index 44b5f61..cc3d198 100644 --- a/opcodes/loongarch-opc.c +++ b/opcodes/loongarch-opc.c @@ -171,7 +171,7 @@ const char *const loongarch_x_normal_name[32] = "lu32i.d %1,%%got64_lo20(%2);" \ "lu52i.d %1,%1,%%got64_hi12(%2);" \ "ld.d %1,%1,0", \ - &LARCH_opts.ase_lp64, \ + &LARCH_opts.ase_gabs, \ &LARCH_opts.ase_gpcr /* got64 pic. */ #define INSN_LA_GOT64_LARGE_PCREL \ @@ -229,7 +229,7 @@ const char *const loongarch_x_normal_name[32] = "lu32i.d %1,%%ie64_lo20(%2);" \ "lu52i.d %1,%1,%%ie64_hi12(%2);" \ "ld.d %1,%1,0", \ - &LARCH_opts.ase_lp64, \ + &LARCH_opts.ase_gabs, \ &LARCH_opts.ase_gpcr /* For LoongArch32/64 cmode=normal. */ @@ -260,7 +260,7 @@ const char *const loongarch_x_normal_name[32] = "ori %1,%1,%%got_lo12(%2);" \ "lu32i.d %1,%%got64_lo20(%2);" \ "lu52i.d %1,%1,%%got64_hi12(%2);", \ - &LARCH_opts.ase_lp64, \ + &LARCH_opts.ase_gabs, \ &LARCH_opts.ase_gpcr #define INSN_LA_TLS_GD32 \ @@ -290,7 +290,7 @@ const char *const loongarch_x_normal_name[32] = "ori %1,%1,%%got_lo12(%2);" \ "lu32i.d %1,%%got64_lo20(%2);" \ "lu52i.d %1,%1,%%got64_hi12(%2);", \ - &LARCH_opts.ase_lp64, \ + &LARCH_opts.ase_gabs, \ &LARCH_opts.ase_gpcr #define INSN_LA_CALL \ @@ -376,27 +376,27 @@ static struct loongarch_opcode loongarch_macro_opcodes[] = { 0, 0, "la.pcrel", "r,la", INSN_LA_PCREL32, 0 }, { 0, 0, "la.pcrel", "r,la", INSN_LA_PCREL64, 0 }, { 0, 0, "la.pcrel", "r,r,la", INSN_LA_PCREL64_LARGE, 0 }, - { 0, 0, "la.got", "r,la", INSN_LA_GOT32, 0 }, { 0, 0, "la.got", "r,la", INSN_LA_GOT32_ABS, 0 }, - { 0, 0, "la.got", "r,la", INSN_LA_GOT64, 0 }, + { 0, 0, "la.got", "r,la", INSN_LA_GOT32, 0 }, { 0, 0, "la.got", "r,la", INSN_LA_GOT64_LARGE_ABS, 0 }, + { 0, 0, "la.got", "r,la", INSN_LA_GOT64, 0 }, { 0, 0, "la.got", "r,r,la", INSN_LA_GOT64_LARGE_PCREL, 0 }, { 0, 0, "la.tls.le", "r,l", INSN_LA_TLS_LE, 0 }, { 0, 0, "la.tls.le", "r,l", INSN_LA_TLS_LE64_LARGE, 0 }, - { 0, 0, "la.tls.ie", "r,l", INSN_LA_TLS_IE32, 0 }, { 0, 0, "la.tls.ie", "r,l", INSN_LA_TLS_IE32_ABS, 0 }, - { 0, 0, "la.tls.ie", "r,l", INSN_LA_TLS_IE64, 0 }, + { 0, 0, "la.tls.ie", "r,l", INSN_LA_TLS_IE32, 0 }, { 0, 0, "la.tls.ie", "r,l", INSN_LA_TLS_IE64_LARGE_ABS, 0 }, + { 0, 0, "la.tls.ie", "r,l", INSN_LA_TLS_IE64, 0 }, { 0, 0, "la.tls.ie", "r,r,l", INSN_LA_TLS_IE64_LARGE_PCREL, 0 }, - { 0, 0, "la.tls.ld", "r,l", INSN_LA_TLS_LD32, 0 }, { 0, 0, "la.tls.ld", "r,l", INSN_LA_TLS_LD32_ABS, 0 }, - { 0, 0, "la.tls.ld", "r,l", INSN_LA_TLS_LD64, 0 }, + { 0, 0, "la.tls.ld", "r,l", INSN_LA_TLS_LD32, 0 }, { 0, 0, "la.tls.ld", "r,l", INSN_LA_TLS_LD64_LARGE_ABS, 0 }, + { 0, 0, "la.tls.ld", "r,l", INSN_LA_TLS_LD64, 0 }, { 0, 0, "la.tls.ld", "r,r,l", INSN_LA_TLS_LD64_LARGE_PCREL, 0 }, - { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD32, 0 }, { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD32_ABS, 0 }, - { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64, 0 }, + { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD32, 0 }, { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64_LARGE_ABS, 0 }, + { 0, 0, "la.tls.gd", "r,l", INSN_LA_TLS_GD64, 0 }, { 0, 0, "la.tls.gd", "r,r,l", INSN_LA_TLS_GD64_LARGE_PCREL, 0 }, { 0, 0, "call36", "la", INSN_LA_CALL, 0 }, { 0, 0, "tail36", "r,la", INSN_LA_TAIL, 0 }, |