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2019-12-11ubsan: cris: signed integer overflowAlan Modra2-19/+21
2019-12-11ubsan: cr16: left shift cannot be represented in type 'int'Alan Modra2-7/+9
2019-12-11ubsan: bfin: shift exponent is too largeAlan Modra2-13/+26
2019-12-11ubsan: arc: shift exponent 32 is too large for 32-bit type 'int'Alan Modra2-1/+6
2019-12-11aarch64 disassembler infinite loopAlan Modra2-0/+8
2019-12-11ubsan: epiphany: left shift of negative valueAlan Modra2-2/+6
2019-12-10PR24960, Memory leak from disassemblerAlan Modra2-0/+64
2019-12-10Use disassemble_info.private_data in place of insn_setsAlan Modra17-27/+46
2019-12-10Remove backup ppc struct dis_private.Alan Modra2-3/+10
2019-12-10s12z-opc.c formatting fixesAlan Modra2-71/+82
2019-12-08S12Z disassembler memory leakAlan Modra2-12/+17
2019-12-05Arm64: simplify Crypto arch extension handlingJan Beulich2-12/+6
2019-12-05PR25249, Memory leak in microblaze-dis.cAlan Modra2-138/+182
2019-12-04x86-64: accept 64-bit LFS/LGS/LSS forms with suffix or operand size specifierJan Beulich3-6/+11
2019-12-04x86/Intel: extend MOVDIRI testingJan Beulich2-1/+5
2019-12-04x86: drop some stray/bogus DefaultSizeJan Beulich3-10/+17
2019-11-22Arm: Change CRC from fpu feature to archititectural extensionMihail Ionescu2-12/+18
2019-11-14x86: drop redundant SYSCALL/SYSRET templatesJan Beulich3-26/+5
2019-11-14x86: fold individual Jump* attributes into a single Jump oneJan Beulich5-14858/+10948
2019-11-14x86: make JumpAbsolute an insn attributeJan Beulich6-26480/+26486
2019-11-14x86: make AnySize an insn attributeJan Beulich5-14486/+14499
2019-11-12RISC-V: Support the INSN_CLASS.*F.* classes for .insn directive.Jim Wilson2-60/+66
2019-11-12[binutils][arm] Update the decoding of MVE VMOV, VMVNMihail Ionescu2-6/+18
2019-11-12x86: fold EsSeg into IsStringJan Beulich6-11272/+11287
2019-11-12x86: eliminate ImmExt abuseJan Beulich6-93/+197
2019-11-12x86: introduce operand type "instance"Jan Beulich7-14199/+14252
2019-11-11Arm64: SVE2's smaxp/sminp require operands 1 and 3 to be the same registerJan Beulich2-2/+7
2019-11-11Arm64: fix build with old glibcJan Beulich2-10/+12
2019-11-08i386: Only check suffix in instruction mnemonicH.J. Lu3-4/+10
2019-11-08x86: convert RegMask and RegBND from bitfield to enumeratorJan Beulich7-14560/+14574
2019-11-08x86: convert RegSIMD and RegMMX from bitfield to enumeratorJan Beulich7-19174/+19187
2019-11-08x86: convert Control/Debug/Test from bitfield to enumeratorJan Beulich7-14001/+14015
2019-11-08x86: convert SReg from bitfield to enumeratorJan Beulich7-13810/+13823
2019-11-08x86: introduce operand type "class"Jan Beulich6-105/+165
2019-11-07[gas][aarch64] Add the v8.6 Data Gathering Hint mnemonic [10/X]Matthew Malcomson3-49/+61
2019-11-07[Patch][binutils][arm] Armv8.6-A Matrix Multiply extension [9/10]Matthew Malcomson2-0/+19
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson6-462/+877
2019-11-07[binutils][arm] BFloat16 enablement [4/X]Matthew Malcomson2-5/+42
2019-11-07[Patch][binutils][arm] Create a new generic coprocessor array [3/10]Matthew Malcomson2-51/+98
2019-11-07[binutils][aarch64] Bfloat16 enablement [2/X]Matthew Malcomson6-68/+373
2019-11-07[gas][aarch64] Armv8.6-a option [1/X]Matthew Malcomson2-0/+8
2019-11-07x86: support further AMD Zen2 instructionsJan Beulich7-4080/+4160
2019-11-07x86: adjust register names printed for MONITOR/MWAITJan Beulich2-16/+20
2019-11-07x86/Intel: drop IgnoreSize from operand-less MOVSD/CMPSD againJan Beulich3-4/+11
2019-11-05x86: fold OP_Mwaitx() into OP_Mwait()Jan Beulich2-24/+11
2019-11-05x86: split MONITORX/MWAITX entriesJan Beulich2-2/+21
2019-11-05x86: consolidate disassembler enum naming a littleJan Beulich2-75/+130
2019-11-04Fix potential array overruns when disassembling corrupt v850 binaries.Nick Clifton2-60/+129
2019-10-30Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv4-3/+15
2019-10-30x86: re-do "shorthand" handlingJan Beulich4-219/+214
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