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2021-10-28ubsan: arm: undefined shiftAlan Modra1-1/+1
2021-10-27RISC-V: Tidy riscv assembler and disassembler.Nelson Chu1-8/+10
2021-10-27opcodes: Fix RPATH not being set for dynamic libbfd dependencyMaciej W. Rozycki5-36/+10
2021-10-24LoongArch opcodes supportliuzhensong10-0/+1637
2021-10-11z80/disassembler: call memory_error_func when appropriateAndrew Burgess1-0/+2
2021-10-11s12z/disassembler: call memory_error_func when appropriateAndrew Burgess1-0/+3
2021-10-07RISC-V: Support aliases for Zbs instructionsPhilipp Tomsich1-0/+4
2021-10-07RISC-V: Add support for Zbs instructionsPhilipp Tomsich1-0/+9
2021-10-07RISC-V: Split Zb[abc] into commented sectionsPhilipp Tomsich1-0/+6
2021-09-28x86: Print {bad} on invalid broadcast in OP_E_memoryCui,Lili1-74/+81
2021-09-27configure: regenerate in all projects that use libtool.m4Nick Alcock2-45/+50
2021-09-25PowerPC: Enable mfppr mfppr32, mtppr and mtppr32 extended mnemonics on POWER5Peter Bergner2-4/+9
2021-09-20riscv: print .2byte or .4byte before an unknown instruction encodingAndrew Burgess2-1/+29
2021-09-13[gdb/tdep] Reset force_thumb in parse_arm_disassembler_optionsTom de Vries1-0/+1
2021-09-08RISC-V: Pretty print values formed with lui and addiw.Jim Wilson1-5/+18
2021-09-06Add a sanity check to the init_nfp6000_mecsr_sec() function in the NFP disass...Yinjun Zhang1-2/+5
2021-09-03pj: asan: out of bounds, ubsan: left shift of negativeAlan Modra1-3/+4
2021-09-02Add support for the haiku operating system. These are the os support patches...Alexander von Gluck IV1-1/+1
2021-09-02Fix the V850 assembler's generation of relocations for the st.b instruction.Nick Clifton2-1/+7
2021-09-01nfp: add validity check of island and meYinjun Zhang1-1/+10
2021-08-30RISC-V: PR28291, Fix the gdb fails that PR27916 caused.Nelson Chu1-2/+2
2021-08-30RISC-V: PR27916, Support mapping symbols.Nelson Chu1-12/+233
2021-08-24FT32: Remove recursion in ft32_opcodeJames Bowman (FTDI-UK)1-114/+115
2021-08-19x86: Put back 3 aborts in OP_E_memoryH.J. Lu1-3/+3
2021-08-19x86: Avoid abort on invalid broadcastH.J. Lu1-4/+4
2021-08-17opcodes: Fix the auxiliary register numbers for ARC HSShahab Vahedi2-2/+6
2021-08-13PR28168: [CSKY] Fix stack overflow in disassemblerLifang Xia1-4/+4
2021-08-11Deprecate a.out support for NetBSD targets.John Ericson1-53/+53
2021-08-10Updated Serbian and Russian translations for various sub-directoriesNick Clifton2-236/+293
2021-08-05[PATCH 1/2] Enable Intel AVX512_FP16 instructionsCui,Lili9-16206/+25260
2021-08-04IBM Z: Remove lpswey parameterAndreas Krebbel2-1/+3
2021-07-27Correct gs264e bfd_mach in mips_arch_choices.Chenghua Xu2-1/+5
2021-07-26PATCH [9/10] arm: add 'pacg' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
2021-07-26PATCH [8/10] arm: add 'autg' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
2021-07-26PATCH [7/10] arm: add 'bxaut' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
2021-07-26PATCH [4/10] arm: add 'pac' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
2021-07-26PATCH [3/10] arm: add 'aut' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
2021-07-26PATCH [2/10] arm: add 'pacbti' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+2
2021-07-26PATCH [1/10] arm: add 'bti' instruction for Armv8.1-M pacbti extensionAndrea Corallo1-0/+5
2021-07-23x86: express unduly set rounding control bits in disassemblyJan Beulich1-37/+53
2021-07-22x86: drop dq{b,d}_modeJan Beulich1-30/+13
2021-07-22x86: drop vex_scalar_w_dq_modeJan Beulich3-51/+41
2021-07-22x86: drop xmm_m{b,w,d,q}_modeJan Beulich4-164/+91
2021-07-22x86: fold duplicate vector register printing codeJan Beulich1-74/+33
2021-07-22x86: drop vex_mode and vex_scalar_modeJan Beulich1-11/+7
2021-07-22x86: correct EVEX.V' handling outside of 64-bit modeJan Beulich1-4/+16
2021-07-22x86: fold duplicate code in MOVSXD_Fixup()Jan Beulich1-16/+10
2021-07-22x86: fold duplicate register printing codeJan Beulich1-105/+14
2021-07-22x86-64: properly bounds-check %bnd<N> in OP_G()Jan Beulich1-1/+1
2021-07-22x86-64: generalize OP_G()'s EVEX.R' handlingJan Beulich1-1/+8