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2019-05-09[binutils][aarch64] Introduce SVE_IMM_ROT3 operand.Matthew Malcomson7-38/+59
2019-05-09[binutils][aarch64] Allow movprfx for SVE2 instructions.Matthew Malcomson2-1/+8
2019-05-09[binutils][aarch64] SVE2 feature extension flags.Matthew Malcomson2-0/+47
2019-05-06Add load-link, store-conditional paired EVA instructionsFaraz Shahbazker3-3/+22
2019-05-01[BINUTILS, AArch64] Enable Transactional Memory ExtensionSudakshina Das6-1086/+1136
2019-04-29S12Z: Opcodes: Fix crash when trying to decode a truncated operation.John Darrington2-1/+5
2019-04-26[MIPS] Add load-link, store-conditional paired instructionsAndrew Bennett2-0/+13
2019-04-24S12Z: Opcodes: Handle bit map operations with non-canonical operands.John Darrington2-3/+6
2019-04-24S12Z: s12z-opc.h: Add extern "C" bracketingJohn Darrington2-1/+13
2019-04-15[binutils, ARM, 16/16] Add support to VLDR and VSTR of system registersAndre Vieira2-1/+59
2019-04-15[binutils, ARM, 15/16] Add support for VSCCLRMAndre Vieira2-0/+38
2019-04-15[opcodes, ARM, 14/16] Add mode availability to coprocessor table entriesAndre Vieira2-413/+443
2019-04-15[binutils, ARM, 13/16] Add support for CLRMAndre Vieira2-2/+21
2019-04-15[binutils, ARM, 12/16] Scalar Low Overhead loop instructions for Armv8.1-M Ma...Andre Vieira2-0/+42
2019-04-15[binutils, ARM, 11/16] New BFCSEL instruction for Armv8.1-M MainlineAndre Vieira2-0/+13
2019-04-15[binutils, ARM, 10/16] BFCSEL infrastructure with new global reloc R_ARM_THM_...Andre Vieira2-0/+22
2019-04-15[binutils, ARM, 9/16] New BFL instruction for Armv8.1-M MainlineAndre Vieira2-0/+6
2019-04-15[binutils, ARM, 8/16] BFL infrastructure with new global reloc R_ARM_THM_BF18Andre Vieira2-0/+22
2019-04-15[binutils, ARM, 7/16] New BFX and BFLX instruction for Armv8.1-M MainlineAndre Vieira2-0/+15
2019-04-15[binutils, ARM, 6/16] New BF instruction for Armv8.1-M MainlineAndre Vieira2-0/+9
2019-04-15[binutils, ARM, 5/16] BF insns infrastructure with new global reloc R_ARM_THM...Andre Vieira2-0/+22
2019-04-15[binutils, ARM, 3/16] BF insns infrastructure with new bfd_reloc_code_real fo...Andre Vieira2-0/+12
2019-04-15[binutils, ARM, 1/16] Add support for Armv8.1-M Mainline CLIAndre Vieira2-0/+5
2019-04-12S12Z: opcodes: Replace "operator" with "optr".John Darrington4-29/+34
2019-04-11[BINUTILS, AArch64, 2/2] Update Store Allocation Tag instructionsSudakshina Das6-165/+186
2019-04-11[BINUTILS, AArch64, 1/2] Add new LDGM/STGM instructionSudakshina Das5-1541/+1572
2019-04-09[MIPS] Add RDHWR with the SEL field for MIPS R6.Robert Suchanek2-0/+5
2019-04-08x86: Consolidate AVX512 BF16 entries in i386-opc.tblH.J. Lu3-282/+34
2019-04-07print_insn_powerpc tidyAlan Modra2-26/+29
2019-04-07PR24421, Wrong brackets in opcodes/arm-dis.cAlan Modra2-213/+219
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo8-4133/+4576
2019-04-05PowerPC bc extended branch mnemonics and "y" hintsAlan Modra2-141/+148
2019-04-05PowerPC disassembler: Don't emit trailing spacesAlan Modra2-4/+16
2019-04-04Add extended mnemonics for bctar. Fix setting of 'at' branch hints.Peter Bergner2-49/+298
2019-03-28PR24390, Don't decode mtfsb field as a cr fieldAlan Modra3-6/+20
2019-03-25Arm: Fix Arm disassembler mapping symbol search.Tamar Christina2-148/+107
2019-03-25AArch64: Have -D override mapping symbol as documented.Tamar Christina2-1/+7
2019-03-25AArch64: Fix AArch64 disassembler mapping symbol searchTamar Christina2-6/+43
2019-03-25AArch64: Fix disassembler bug with out-of-order sectionsTamar Christina2-1/+11
2019-03-19ix86: Disable AVX512F when disabling AVX2H.J. Lu3-7/+14
2019-03-18x86: Optimize EVEX vector load/store instructionsH.J. Lu3-12/+19
2019-03-12Add missing changelogs for previous commits.Andreas Krebbel1-0/+9
2019-03-12S/390: arch13: Adjust to recent changesAndreas Krebbel1-5/+5
2019-03-12S/390: arch13: Add instruction descriptionsAndreas Krebbel1-101/+115
2019-02-08Add missing ChangeLog files for previous patch.Jim Wilson1-0/+5
2019-02-08RISC-V: Compress 3-operand beq/bne against x0.Jim Wilson1-0/+2
2019-02-07Arm: Backport hlt to all architectures.Tamar Christina2-1/+6
2019-02-07AArch64: Add verifier for By elem Single and Double sized instructions.Tamar Christina4-9/+46
2019-02-07Updated Swedish translation for the opcodes sub-directoryNick Clifton2-308/+352
2019-01-31S/390: Implement instruction set extensionsAndreas Krebbel4-0/+117
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