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authorFaraz Shahbazker <fshahbazker@wavecomp.com>2019-04-28 18:21:00 -0700
committerFaraz Shahbazker <fshahbazker@wavecomp.com>2019-05-06 06:43:32 -0700
commit41cee0897b670168e0d6f455c9bc45c73f8023df (patch)
tree90f15ebdf438ae1956dc5a3d7eea35c64ae41a10 /opcodes
parentbe0d3bbbcdbdba83f74d8ad1be6c4c759255af0b (diff)
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Add load-link, store-conditional paired EVA instructions
Add paired load-link and store-conditional instructions to the EVA ASE for MIPS32R6[1]. These instructions are optional within the EVA ASE. Their presence is indicated by the XNP bit in the Config5 register. [1] "MIPS Architecture for Programmers Volume II-A: The MIPS32 Instruction Set Manual", Imagination Technologies Ltd., Document Number: MD00086, Revision 6.06, December 15, 2016, Section 3.2 "Alphabetical List of Instructions", pp. 230-231, pp. 357-360. gas/ * config/tc-mips.c (mips_set_ase): Handle ASE_EVA_R6. (macro) <M_LLWPE_AB, M_SCWPE_AB>: New cases. (mips_after_parse_args): Translate EVA to EVA_R6. * testsuite/gas/mips/ase-errors-1.s: Add new instructions. * testsuite/gas/mips/eva.s: Likewise. * testsuite/gas/mips/ase-errors-1.l: Check errors for new instructions. * testsuite/gas/mips/mipsr6@eva.d: Check new test cases. include/ * opcode/mips.h (ASE_EVA_R6): New macro. (M_LLWPE_AB, M_SCWPE_AB): New enum values. opcodes/ * mips-dis.c (mips_calculate_combination_ases): Add ISA argument and set ASE_EVA_R6 appropriately. (set_default_mips_dis_options): Pass ISA to above. (parse_mips_dis_option): Likewise. * mips-opc.c (EVAR6): New macro. (mips_builtin_opcodes): Add llwpe, scwpe. Derived from patch authored by Andrew Bennett <andrew.bennett@imgtec.com>
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog10
-rw-r--r--opcodes/mips-dis.c10
-rw-r--r--opcodes/mips-opc.c5
3 files changed, 22 insertions, 3 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 2328f18..6c4d1d9 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,3 +1,13 @@
+2019-05-06 Andrew Bennett <andrew.bennett@imgtec.com>
+ Faraz Shahbazker <fshahbazker@wavecomp.com>
+
+ * mips-dis.c (mips_calculate_combination_ases): Add ISA
+ argument and set ASE_EVA_R6 appropriately.
+ (set_default_mips_dis_options): Pass ISA to above.
+ (parse_mips_dis_option): Likewise.
+ * mips-opc.c (EVAR6): New macro.
+ (mips_builtin_opcodes): Add llwpe, scwpe.
+
2019-05-01 Sudakshina Das <sudi.das@arm.com>
* aarch64-asm-2.c: Regenerated.
diff --git a/opcodes/mips-dis.c b/opcodes/mips-dis.c
index 0dc437e..5bf33d9 100644
--- a/opcodes/mips-dis.c
+++ b/opcodes/mips-dis.c
@@ -829,7 +829,7 @@ mips_convert_abiflags_ases (unsigned long afl_ases)
/* Calculate combination ASE flags from regular ASE flags. */
static unsigned long
-mips_calculate_combination_ases (unsigned long opcode_ases)
+mips_calculate_combination_ases (int opcode_isa, unsigned long opcode_ases)
{
unsigned long combination_ases = 0;
@@ -837,6 +837,10 @@ mips_calculate_combination_ases (unsigned long opcode_ases)
combination_ases |= ASE_XPA_VIRT;
if ((opcode_ases & (ASE_MIPS16E2 | ASE_MT)) == (ASE_MIPS16E2 | ASE_MT))
combination_ases |= ASE_MIPS16E2_MT;
+ if ((opcode_ases & ASE_EVA)
+ && ((opcode_isa & INSN_ISA_MASK) == ISA_MIPS64R6
+ || (opcode_isa & INSN_ISA_MASK) == ISA_MIPS32R6))
+ combination_ases |= ASE_EVA_R6;
return combination_ases;
}
@@ -909,7 +913,7 @@ set_default_mips_dis_options (struct disassemble_info *info)
mips_ase |= ASE_MDMX;
}
#endif
- mips_ase |= mips_calculate_combination_ases (mips_ase);
+ mips_ase |= mips_calculate_combination_ases (mips_isa, mips_ase);
}
/* Parse an ASE disassembler option and set the corresponding global
@@ -997,7 +1001,7 @@ parse_mips_dis_option (const char *option, unsigned int len)
if (parse_mips_ase_option (option))
{
- mips_ase |= mips_calculate_combination_ases (mips_ase);
+ mips_ase |= mips_calculate_combination_ases (mips_isa, mips_ase);
return;
}
diff --git a/opcodes/mips-opc.c b/opcodes/mips-opc.c
index 8db2952..64b13c8 100644
--- a/opcodes/mips-opc.c
+++ b/opcodes/mips-opc.c
@@ -392,6 +392,7 @@ decode_mips_operand (const char *p)
/* MIPS Enhanced VA Scheme. */
#define EVA ASE_EVA
+#define EVAR6 ASE_EVA_R6
/* TLB invalidate instruction support. */
#define TLBINV ASE_EVA
@@ -2638,6 +2639,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"lhe", "t,A(b)", 0, (int) M_LHE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"lle", "t,+j(b)", 0x7c00002e, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lle", "t,A(b)", 0, (int) M_LLE_AB, INSN_MACRO, 0, 0, EVA, 0 },
+{"llwpe", "t,d,s", 0x7c00006e, 0xfc0007ff, WR_1|WR_2|RD_3|LM, 0, 0, EVAR6, 0 },
+{"llwpe", "t,d,A(b)", 0, (int) M_LLWPE_AB, INSN_MACRO, 0, 0, EVAR6, 0 },
{"lwe", "t,+j(b)", 0x7c00002f, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, 0 },
{"lwe", "t,A(b)", 0, (int) M_LWE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"lwle", "t,+j(b)", 0x7c000019, 0xfc00007f, WR_1|RD_3|LM, 0, 0, EVA, I37 },
@@ -2648,6 +2651,8 @@ const struct mips_opcode mips_builtin_opcodes[] =
{"sbe", "t,A(b)", 0, (int) M_SBE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"sce", "t,+j(b)", 0x7c00001e, 0xfc00007f, MOD_1|RD_3|SM, 0, 0, EVA, 0 },
{"sce", "t,A(b)", 0, (int) M_SCE_AB, INSN_MACRO, 0, 0, EVA, 0 },
+{"scwpe", "t,d,s", 0x7c00005e, 0xfc0007ff, MOD_1|RD_2|RD_3|SM, 0, 0, EVAR6, 0 },
+{"scwpe", "t,d,A(b)", 0, (int) M_SCWPE_AB, INSN_MACRO, 0, 0, EVAR6, 0 },
{"she", "t,+j(b)", 0x7c00001d, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 },
{"she", "t,A(b)", 0, (int) M_SHE_AB, INSN_MACRO, 0, 0, EVA, 0 },
{"swe", "t,+j(b)", 0x7c00001f, 0xfc00007f, RD_1|RD_3|SM, 0, 0, EVA, 0 },