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2020-04-20[AArch64, Binutils] Add missing TSB instructionSudakshina Das10-1376/+1422
2020-04-20[AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das5-1370/+1369
2020-04-17[PATCH v2] binutils: arm: Fix disassembly of conditional VDUPs.Fredrik Strupe2-10/+53
2020-04-16cpu,gas,opcodes: support for eBPF JMP32 instruction classDavid Faust5-13/+515
2020-04-07Add support for intel TSXLDTRK instructions$Cui,Lili7-4154/+4234
2020-04-02Add support for intel SERIALIZE instructionLiliCui7-4151/+4205
2020-03-26Re: H8300 use of uninitialised valueAlan Modra4-126/+152
2020-03-26Re: ARC: Use of uninitialised valueAlan Modra2-2/+6
2020-03-25Uninitialised memory read in z80-dis.cAlan Modra2-0/+5
2020-03-22H8300 use of uninitialised valueAlan Modra2-6/+33
2020-03-22ARC: Use of uninitialised valueAlan Modra2-3/+10
2020-03-22NS32K arg_bufs uninitialisedAlan Modra2-9/+17
2020-03-22s12z disassembler tidyAlan Modra3-315/+760
2020-03-20metag uninitialized memory readAlan Modra2-2/+13
2020-03-20NDS32 disassembly of odd sized sectionsAlan Modra2-9/+22
2020-03-20PowerPC disassembly of odd sized sectionsAlan Modra2-10/+25
2020-03-17Replace a couple of assertions in the BFD library that can be triggered by at...Nick Clifton1-0/+5
2020-03-17Fix a small set of Z80 problems.Sergey Belyashov1-19/+8
2020-03-13x86-64: correct mis-named X86_64_0D enumeratorJan Beulich2-3/+8
2020-03-09x86: Also pass -P to $(CPP) when processing i386-opc.tblH.J. Lu3-2/+7
2020-03-09x86: use template for AVX512 integer comparison insnsJan Beulich3-80/+48
2020-03-09x86: use template for XOP integer comparison, shift, and rotate insnsJan Beulich3-268/+187
2020-03-09x86: use template for AVX/AVX512 floating point comparison insnsJan Beulich3-3877/+4305
2020-03-09x86: use template for SSE floating point comparison insnsJan Beulich4-208/+165
2020-03-09x86: allow opcode templates to be templatedJan Beulich4-151/+298
2020-03-06x86: reduce amount of various VCVT* templatesJan Beulich3-237/+93
2020-03-06x86: drop/replace IgnoreSizeJan Beulich3-1602/+1608
2020-03-06x86: don't accept FI{LD,STP,STTP}LL in Intel syntax modeJan Beulich3-9/+14
2020-03-06x86: replace NoRex64 on VEX-encoded insnsJan Beulich3-50/+62
2020-03-06x86: drop Rex64 attributeJan Beulich5-6598/+6603
2020-03-06x86: correct MPX insn w/o base or index encoding in 16-bit modeJan Beulich2-4/+19
2020-03-06x86: add missing IgnoreSizeJan Beulich3-36/+56
2020-03-06x86: refine TPAUSE and UMWAITJan Beulich3-10/+48
2020-03-04x86: support VMGEXITJan Beulich7-4100/+4148
2020-03-03x86: Replace IgnoreSize/DefaultSize with MnemonicSizeH.J. Lu5-10857/+10874
2020-03-03The patch fixed invalid compilation of instruction LD IY,(HL) and disassemble...Sergey Belyashov2-2/+8
2020-03-03x86: Allow integer conversion without suffix in AT&T syntaxH.J. Lu3-20/+189
2020-02-26Indent labelsAlan Modra10-24/+36
2020-02-25[ARC][committed] Update int_vector_base aux register.Claudiu Zissulescu2-2/+6
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu2-1/+6
2020-02-19RISC-V: Convert the ADD/ADDI to the compressed MV/LI if RS1 is zero.Jim Wilson2-0/+7
2020-02-17x86: Remove CpuABM and add CpuPOPCNTH.J. Lu6-2822/+2848
2020-02-17x86: fold certain VCVT{,U}SI2S{S,D} templatesJan Beulich3-133/+38
2020-02-17x86: fold AddrPrefixOpReg templatesJan Beulich3-201/+52
2020-02-17x86/Intel: improve diagnostics for ambiguous VCVT* operandsJan Beulich3-33/+194
2020-02-16x86: Don't disable SSE3 when disabling SSE4aH.J. Lu3-2/+7
2020-02-17Re: x86: Don't disable SSE4a when disabling SSE4Alan Modra2-2/+6
2020-02-16x86: Don't disable SSE4a when disabling SSE4H.J. Lu3-4/+9
2020-02-14Remove Intel syntax comments on movsx and movzxH.J. Lu2-3/+7
2020-02-14x86: replace adhoc (partly wrong) ambiguous operand checking for MOVSX/MOVZXJan Beulich3-118/+21
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