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author | Fredrik Strupe <fredrik@strupe.net> | 2020-04-17 17:25:19 +0100 |
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committer | Nick Clifton <nickc@redhat.com> | 2020-04-17 17:25:19 +0100 |
commit | e409955ddcc33743044f217a3cc0541e0e6211b7 (patch) | |
tree | 5035e7c39e0a85db570823c1fa1925d3326f11ba /opcodes | |
parent | 0203cad215219c3f78c5dff246fbc189946d06ce (diff) | |
download | gdb-e409955ddcc33743044f217a3cc0541e0e6211b7.zip gdb-e409955ddcc33743044f217a3cc0541e0e6211b7.tar.gz gdb-e409955ddcc33743044f217a3cc0541e0e6211b7.tar.bz2 |
[PATCH v2] binutils: arm: Fix disassembly of conditional VDUPs.
VDUP (neon) instructions can be conditional, but this is not taken into
account in the current master. This commit fixes that by i) fixing the
VDUP instruction masks and ii) adding logic for disassembling
conditional neon instructions.
opcodes * arm-dis.c (neon_opcodes): Fix VDUP instruction masks.
(print_insn_neon): Support disassembly of conditional
instructions.
binutils* testsuite/binutils-all/arm/vdup-cond.d: New test for testing that
conditional VDUP instructions are disassembled correctly.
* testsuite/binutils-all/arm/vdup-cond.s: New file used by
vdup-cond.d.
* testsuite/binutils-all/arm/vdup-thumb.d: New test for testing
that VDUP instructions (which are conditional in A32) can be
disassembled in thumb mode.
* testsuite/binutils-all/arm/vdup-cond.s: New file used by
vdup-thumb.d.
Diffstat (limited to 'opcodes')
-rw-r--r-- | opcodes/ChangeLog | 6 | ||||
-rw-r--r-- | opcodes/arm-dis.c | 57 |
2 files changed, 53 insertions, 10 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 1877338..e3233f0 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2020-04-17 Fredrik Strupe <fredrik@strupe.net> + + * arm-dis.c (neon_opcodes): Fix VDUP instruction masks. + (print_insn_neon): Support disassembly of conditional + instructions. + 2020-02-16 David Faust <david.faust@oracle.com> * bpf-desc.c: Regenerate. diff --git a/opcodes/arm-dis.c b/opcodes/arm-dis.c index b926b65..79a3dc6 100644 --- a/opcodes/arm-dis.c +++ b/opcodes/arm-dis.c @@ -1494,17 +1494,17 @@ static const struct opcode32 neon_opcodes[] = /* Data transfer between ARM and NEON registers. */ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0e800b10, 0x1ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, + 0x0e800b10, 0x0ff00f70, "vdup%c.32\t%16-19,7D, %12-15r"}, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0e800b30, 0x1ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, + 0x0e800b30, 0x0ff00f70, "vdup%c.16\t%16-19,7D, %12-15r"}, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0ea00b10, 0x1ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, + 0x0ea00b10, 0x0ff00f70, "vdup%c.32\t%16-19,7Q, %12-15r"}, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0ea00b30, 0x1ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, + 0x0ea00b30, 0x0ff00f70, "vdup%c.16\t%16-19,7Q, %12-15r"}, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0ec00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, + 0x0ec00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7D, %12-15r"}, {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), - 0x0ee00b10, 0x1ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, + 0x0ee00b10, 0x0ff00f70, "vdup%c.8\t%16-19,7Q, %12-15r"}, /* Move data element to all lanes. */ {ARM_FEATURE_COPROC (FPU_NEON_EXT_V1), @@ -9032,13 +9032,51 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) || (given & 0xff000000) == 0xfc000000) ; /* vdup is also a valid neon instruction. */ - else if ((given & 0xff910f5f) != 0xee800b10) + else if ((given & 0xff900f5f) != 0xee800b10) return FALSE; } for (insn = neon_opcodes; insn->assembler; insn++) { - if ((given & insn->mask) == insn->value) + unsigned long cond_mask = insn->mask; + unsigned long cond_value = insn->value; + int cond; + + if (thumb) + { + if ((cond_mask & 0xf0000000) == 0) { + /* For the entries in neon_opcodes, an opcode mask/value with + the high 4 bits equal to 0 indicates a conditional + instruction. For thumb however, we need to include those + bits in the instruction matching. */ + cond_mask |= 0xf0000000; + /* Furthermore, the thumb encoding of a conditional instruction + will have the high 4 bits equal to 0xe. */ + cond_value |= 0xe0000000; + } + if (ifthen_state) + cond = IFTHEN_COND; + else + cond = COND_UNCOND; + } + else + { + if ((given & 0xf0000000) == 0xf0000000) + { + /* If the instruction is unconditional, update the mask to only + match against unconditional opcode values. */ + cond_mask |= 0xf0000000; + cond = COND_UNCOND; + } + else + { + cond = (given >> 28) & 0xf; + if (cond == 0xe) + cond = COND_UNCOND; + } + } + + if ((given & cond_mask) == cond_value) { signed long value_in_comment = 0; bfd_boolean is_unpredictable = FALSE; @@ -9060,8 +9098,7 @@ print_insn_neon (struct disassemble_info *info, long given, bfd_boolean thumb) /* Fall through. */ case 'c': - if (thumb && ifthen_state) - func (stream, "%s", arm_conditional[IFTHEN_COND]); + func (stream, "%s", arm_conditional[cond]); break; case 'A': |