| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-02-20 | kvx: enable magic immediates for integer multiply-accumulate and CMOVE* | Paul Iannetta | 1 | -39/+1490 |
| 2024-02-20 | kvx: gas: rename: or -> ior, xor -> eor | Paul Iannetta | 1 | -2396/+5257 |
| 2024-02-20 | kvx: gas: move the splat modifier to the immediate | Paul Iannetta | 1 | -1083/+1134 |
| 2024-02-19 | aarch64: Add support for the id_aa64isar3_el1 system register | Yury Khrustalev | 1 | -0/+1 |
| 2024-02-16 | x86/APX: drop stray IgnoreSize | Jan Beulich | 2 | -22/+22 |
| 2024-02-16 | x86: don't use VexWIG in SSE2AVX templates | Jan Beulich | 2 | -8/+8 |
| 2024-02-16 | x86: drop redundant Xmmword | Jan Beulich | 1 | -8/+8 |
| 2024-02-15 | objdump, as: add callx support for BPF CPU v1 | Will Hawkins | 2 | -1/+5 |
| 2024-02-14 | arc: Put DBNZ instruction to a separate class | Yuriy Kolerov | 3 | -1/+7 |
| 2024-02-09 | PowerPC: Add support for Power11 options | Peter Bergner | 1 | -1/+11 |
| 2024-02-09 | x86/APX: with REX2 map 1 doesn't "chain" to maps 2 or 3 | Jan Beulich | 1 | -7/+5 |
| 2024-02-09 | x86/APX: V{BROADCAST,EXTRACT,INSERT}{F,I}128 can also be expressed | Jan Beulich | 2 | -201/+285 |
| 2024-02-09 | x86/APX: VROUND{P,S}{S,D} encodings require AVX512{F,VL} | Jan Beulich | 2 | -6/+6 |
| 2024-02-09 | x86: change type of Dwarf2 register numbers in register table | Jan Beulich | 1 | -2/+2 |
| 2024-01-29 | bpf: there is no ldinddw nor ldabsdw instructions | Jose E. Marchesi | 2 | -4/+5 |
| 2024-01-26 | aarch64: move SHA512 instructions to +sha3 | Andrew Carlotti | 1 | -5/+5 |
| 2024-01-26 | x86/APX: TILE{RELEASE,ZERO} have no EVEX encodings | Jan Beulich | 2 | -2/+11 |
| 2024-01-26 | x86/APX: no need to have decode go through x86_64_table[] | Jan Beulich | 3 | -76/+27 |
| 2024-01-26 | x86/APX: optimize MOVBE | Jan Beulich | 2 | -36/+38 |
| 2024-01-26 | LoongArch: gas: Add support for s9 register | mengqinggang | 1 | -0/+9 |
| 2024-01-24 | aarch64: Eliminate unused variable warnings with -DNDEBUG | Andrew Carlotti | 3 | -8/+8 |
| 2024-01-22 | Updated Serbian translations for th bfd, gold and opcodes directories | Nick Clifton | 1 | -312/+371 |
| 2024-01-22 | opcodes: tic4x_disassemble swap xcalloc arguments | Mark Wielaard | 1 | -2/+2 |
| 2024-01-19 | x86-64: Dwarf2 register numbers for %bnd<N> | Jan Beulich | 2 | -8/+8 |
| 2024-01-19 | x86/APX: VROUND{P,S}{S,D} can generally be encoded | Jan Beulich | 2 | -147/+203 |
| 2024-01-19 | x86/APX: be consistent with insn suffixes | Jan Beulich | 1 | -5/+5 |
| 2024-01-19 | x86: drop redundant EVex128 from PUSH2/POP2 | Jan Beulich | 1 | -4/+4 |
| 2024-01-19 | x86: support APX forms of U{RD,WR}MSR | Jan Beulich | 5 | -12/+55 |
| 2024-01-18 | Add note to translators not to translate z/Architecture | Nick Clifton | 1 | -0/+1 |
| 2024-01-18 | Updated translations for various sub-directories | Nick Clifton | 4 | -1512/+1762 |
| 2024-01-15 | Change version to 2.42.50 and regenerate files | Nick Clifton | 3 | -117/+130 |
| 2024-01-15 | Add markers for 2.42 branch | Nick Clifton | 1 | -0/+4 |
| 2024-01-15 | aarch64: rcpc3: Regenerate aarch64-*-2.c files | Victor Do Nascimento | 3 | -2870/+2977 |
| 2024-01-15 | aarch64: rcpc3: Add FP load/store insns | Victor Do Nascimento | 1 | -0/+4 |
| 2024-01-15 | aarch64: rcpc3: Add integer load/store insns | Victor Do Nascimento | 1 | -0/+5 |
| 2024-01-15 | aarch64: rcpc3: Define RCPC3_INSN macro | Victor Do Nascimento | 1 | -0/+2 |
| 2024-01-15 | aarch64: rcpc3: add support in general_constraint_met_p | Victor Do Nascimento | 1 | -0/+40 |
| 2024-01-15 | aarch64: rcpc3: New RCPC3_ADDR operand types | Victor Do Nascimento | 2 | -1/+20 |
| 2024-01-15 | aarch64: rcpc3: Define address operand fields and inserter/extractors | Victor Do Nascimento | 6 | -1/+150 |
| 2024-01-15 | aarch64: rcpc3: Create implicit load/store size calc function | Victor Do Nascimento | 1 | -0/+22 |
| 2024-01-15 | aarch64: rcpc3: Add +rcpc3 architectural feature support flag | Victor Do Nascimento | 1 | -0/+4 |
| 2024-01-15 | aarch64: Fix tlbi and tlbip instructions | Andrew Carlotti | 2 | -141/+93 |
| 2024-01-15 | aarch64: Refactor aarch64_sys_ins_reg_supported_p | Andrew Carlotti | 1 | -377/+204 |
| 2024-01-15 | Add generated source files and fix thinko in aarch64-asm.c | Nick Clifton | 4 | -564/+1056 |
| 2024-01-15 | aarch64: Add SVE2.1 Contiguous load/store instructions. | Srinath Parvathaneni | 4 | -2/+59 |
| 2024-01-15 | PATCH 5/6][Binutils] aarch64: Add SVE2.1 fmin and fmax instructions. | Srinath Parvathaneni | 1 | -0/+12 |
| 2024-01-15 | aarch64: Add SVE2.1 dupq, eorqv and extq instructions. | Srinath Parvathaneni | 6 | -0/+73 |
| 2024-01-15 | aarch64: Add support for FEAT_SVE2p1. | Srinath Parvathaneni | 3 | -0/+53 |
| 2024-01-15 | aarch64: Add support for FEAT_SME2p1 instructions. | Srinath Parvathaneni | 7 | -0/+274 |
| 2024-01-15 | aarch64: Add support for FEAT_B16B16 instructions. | Srinath Parvathaneni | 1 | -0/+31 |
