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2022-04-04opcodes/i386: partially implement disassembler style supportAndrew Burgess2-24/+46
2022-04-04opcodes/riscv: implement style support in the disassemblerAndrew Burgess2-72/+122
2022-04-04objdump/opcodes: add syntax highlighting to disassembler outputAndrew Burgess2-1/+17
2022-03-31x86: Remove bfd_arch_l1om and bfd_arch_k1omH.J. Lu3-4/+2
2022-03-31aarch64: Relax check for RNG system registersRichard Sandiford1-1/+1
2022-03-29RISC-V: correct FCVT.Q.L[U]Jan Beulich1-2/+2
2022-03-25libtool.m4: fix the NM="/nm/over/here -B/option/with/path" caseNick Alcock1-7/+13
2022-03-24x86: drop L1OM special case from disassemblerJan Beulich1-6/+2
2022-03-20gas:LoongArch: Fix segment error in compilation due to too long symbol name.liuzhensong1-5/+10
2022-03-20ubsan: loongarch : signed integer shift overflow.liuzhensong1-6/+9
2022-03-18x86: also fold remaining multi-vector-size shift insnsJan Beulich2-375/+67
2022-03-18x86: drop stray CheckRegSize from VEXTRACT{F,I}32X4Jan Beulich2-4/+4
2022-03-18x86: fold certain AVX2 templates into their AVX counterpartsJan Beulich2-2284/+558
2022-03-18RISC-V: Cache management instructionsTsukasa OI1-0/+6
2022-03-18RISC-V: Prefetch hint instructions and operand setTsukasa OI2-0/+7
2022-03-17x86: never set i386_cpu_flags' "unused" fieldJan Beulich3-5/+10
2022-03-17x86: unify CPU flag on/off processingJan Beulich2-22/+11
2022-03-17x86: drop L1OM/K1OM support from gasJan Beulich4-5843/+5813
2022-03-17x86: assorted IAMCU CPU checking fixesJan Beulich2-2/+2
2022-03-16opcodes: handle bfd_amdgcn_arch in configure scriptSimon Marchi3-0/+7
2022-03-16Delete PowerPC macro insn supportAlan Modra1-18/+0
2022-03-16PowerPC SPE/SPE2 aliases in powerpc_macrosAlan Modra1-30/+27
2022-03-16PowerPC VLE extended instructions in powerpc_macrosAlan Modra1-13/+10
2022-03-16PowerPC32 extended instructions in powerpc_macrosAlan Modra1-25/+296
2022-03-16PowerPC64 extended instructions in powerpc_macrosAlan Modra1-19/+245
2022-03-14PR28959, obdump doesn't disassemble mftb instructionAlan Modra1-2/+3
2022-03-06MIPS/opcodes: Fix alias annotation for branch instructionsMaciej W. Rozycki3-7/+16
2022-02-25RISC-V: Fix mask for some fcvt instructionsTsukasa OI1-4/+4
2022-02-17Updated Serbian translations for the bfd, gold, ld and opcodes directoriesNick Clifton2-235/+275
2022-02-15x86: Add has_sib to struct instr_infoH.J. Lu1-8/+9
2022-02-14microblaze: fix fsqrt collicion to build on glibc-2.35Sergei Trofimovich3-2/+8
2022-01-24Update Bulgarian, French, Romaniam and Ukranian translation for some of the s...Nick Clifton4-923/+2834
2022-01-23Regenerate Makefile.in files with automake 1.15.1H.J. Lu1-1/+0
2022-01-23Regenerate configure files with autoconf 2.69H.J. Lu1-15/+3
2022-01-22Change version number to 2.38.50 and regenerate filesNick Clifton3-14/+31
2022-01-22Add markers for 2.38 branchNick Clifton1-0/+4
2022-01-21drop old unused stamp-h.in fileMike Frysinger1-1/+0
2022-01-17Update the config.guess and config.sub files from the master repository and r...Nick Clifton3-208/+244
2022-01-17x86: adjust struct instr_info field typesJan Beulich1-36/+39
2022-01-17x86: drop index16 fieldJan Beulich1-5/+3
2022-01-17x86: drop most Intel syntax register name arraysJan Beulich1-230/+119
2022-01-17x86: fold variables in memory operand index handlingJan Beulich1-19/+15
2022-01-17x86: constify disassembler static dataJan Beulich1-58/+58
2022-01-14x86: drop ymmxmm_modeJan Beulich1-16/+0
2022-01-14x86: share yet more VEX table entries with EVEX decodingJan Beulich4-209/+69
2022-01-14x86: consistently use scalar_mode for AVX512-FP16 scalar insnsJan Beulich2-31/+31
2022-01-14x86: record further wrong uses of EVEX.bJan Beulich1-0/+8
2022-01-14x86: reduce AVX512 FP set of insns decoded through vex_w_table[]Jan Beulich5-268/+42
2022-01-14x86: reduce AVX512-FP16 set of insns decoded through vex_w_table[]Jan Beulich4-137/+77
2022-01-06aarch64: Add support for new SME instructionsRichard Sandiford2-302/+338
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