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2020-01-03Arm64: correct address index operands for LD1RO{H,W,D}Jan Beulich2-7/+12
Just like their LD1RQ{H,W,D} counterparts, as per the specification the index registers get scaled by element size.
2020-01-03Arm64: correct {su,us}dot SIMD encodingsJan Beulich2-3/+8
According to the specification these permit the Q bit to control the vector length operated on, and hence this bit should not already be set in the opcode table entries (it rather needs setting dynamically). Note how the test case output did also not match its input. Besides correcting the test case also extend it to cover both forms.
2020-01-03Arm64: correct uzp{1,2} mnemonicsJan Beulich3-4/+10
According to the specification, and in line with the pre-existing predicate forms, the mnemonics do not include an 'i'.
2020-01-03Arm64: correct 64-bit element fmmla encodingJan Beulich3-46/+52
There's just one bit of difference to the 32-bit element form, as per the documentation.
2020-01-02Add support for the GBZ80, Z180, and eZ80 variants of the Z80 architecure. ↵Sergey Belyashov3-532/+878
Add an ELF based target for these as well. PR 25224 bfd * Makefile.am: Add z80-elf target support. * configure.ac: Likewise. * targets.c: Likewise. * config.bfd: Add z80-elf target support and new arches: ez80 and z180. * elf32-z80.c: New file. * archures.c: Add new z80 architectures: eZ80 and Z180. * coffcode.h: Likewise. * cpu-z80.c: Likewise. * bfd-in2.h: Likewise plus additional Z80 relocations. * coff-z80.c: Add new relocations for Z80 target and local label check. gas * config/tc-z80.c: Add new architectures: Z180 and eZ80. Add support for assembler code generated by SDCC. Add new relocation types. Add z80-elf target support. * config/tc-z80.h: Add z80-elf target support. Enable dollar local labels. Local labels starts from ".L". * testsuite/gas/all/fwdexp.d: Fix failure due to symbol conflict. * testsuite/gas/all/fwdexp.s: Likewise. * testsuite/gas/z80/suffix.d: Fix failure on ELF target. * testsuite/gas/z80/z80.exp: Add new tests * testsuite/gas/z80/dollar.d: New file. * testsuite/gas/z80/dollar.s: New file. * testsuite/gas/z80/ez80_adl_all.d: New file. * testsuite/gas/z80/ez80_adl_all.s: New file. * testsuite/gas/z80/ez80_adl_suf.d: New file. * testsuite/gas/z80/ez80_isuf.s: New file. * testsuite/gas/z80/ez80_z80_all.d: New file. * testsuite/gas/z80/ez80_z80_all.s: New file. * testsuite/gas/z80/ez80_z80_suf.d: New file. * testsuite/gas/z80/r800_extra.d: New file. * testsuite/gas/z80/r800_extra.s: New file. * testsuite/gas/z80/r800_ii8.d: New file. * testsuite/gas/z80/r800_z80_doc.d: New file. * testsuite/gas/z80/z180.d: New file. * testsuite/gas/z80/z180.s: New file. * testsuite/gas/z80/z180_z80_doc.d: New file. * testsuite/gas/z80/z80_doc.d: New file. * testsuite/gas/z80/z80_doc.s: New file. * testsuite/gas/z80/z80_ii8.d: New file. * testsuite/gas/z80/z80_ii8.s: New file. * testsuite/gas/z80/z80_in_f_c.d: New file. * testsuite/gas/z80/z80_in_f_c.s: New file. * testsuite/gas/z80/z80_op_ii_ld.d: New file. * testsuite/gas/z80/z80_op_ii_ld.s: New file. * testsuite/gas/z80/z80_out_c_0.d: New file. * testsuite/gas/z80/z80_out_c_0.s: New file. * testsuite/gas/z80/z80_reloc.d: New file. * testsuite/gas/z80/z80_reloc.s: New file. * testsuite/gas/z80/z80_sli.d: New file. * testsuite/gas/z80/z80_sli.s: New file. ld * Makefile.am: Add new target z80-elf * configure.tgt: Likewise. * emultempl/z80.em: Add support for eZ80 and Z180 architectures. * emulparams/elf32z80.sh: New file. * emultempl/z80elf.em: Likewise. * testsuite/ld-z80/arch_ez80_adl.d: Likewise. * testsuite/ld-z80/arch_ez80_z80.d: Likewise. * testsuite/ld-z80/arch_r800.d: Likewise. * testsuite/ld-z80/arch_z180.d: Likewise. * testsuite/ld-z80/arch_z80.d: Likewise. * testsuite/ld-z80/comb_arch_ez80_z80.d: Likewise. * testsuite/ld-z80/comb_arch_z180.d: Likewise. * testsuite/ld-z80/labels.s: Likewise. * testsuite/ld-z80/relocs.s: Likewise. * testsuite/ld-z80/relocs_b_ez80.d: Likewise. * testsuite/ld-z80/relocs_b_z80.d: Likewise. * testsuite/ld-z80/relocs_f_z80.d: Likewise. * testsuite/ld-z80/z80.exp: Likewise. opcodes * z80-dis.c: Add support for eZ80 and Z80 instructions.
2020-01-01Re: Update year range in copyright notice of binutils filesAlan Modra1-0/+4
Add the ChangeLog entry.
2020-01-01Update year range in copyright notice of binutils filesAlan Modra275-279/+279
2020-01-01ChangeLog rotationAlan Modra2-2444/+2458
2019-12-30Re: Usage of unitialized heap in tic4x_print_condAlan Modra2-1/+6
PR 25319 * tic4x-dis.c (tic4x_print_cond): Correct order of xcalloc args.
2019-12-29ubsan: sparc: left shift cannot be represented in type 'int'Alan Modra2-9/+12
* sparc-dis.c (SEX): Don't use left and right shift to sign extend. (compare_opcodes): Avoid signed shift left overflow. (print_insn_sparc): Likewise.
2019-12-29Usage of unitialized heap in tic4x_print_condAlan Modra2-1/+6
PR 25319 * tic4x-dis.c (tic4x_print_cond): Init all of condtable.
2019-12-27x86-64: fix Intel64 handling of branch with data16 prefixJan Beulich2-3/+14
The expectation of x86-64-branch-3 for "call" / "jmp" with an obvious direct destination to translate to an indirect _far_ branch is plain wrong. The operand size prefix should have no effect at all on the interpretation of the operand. The main underlying issue here is that the Intel64 templates of the direct branches don't include Disp16, yet various assumptions exist that it would always be there when there's also Disp32/Disp32S, toggled by the operand size prefix (which is being ignored by direct branches in Intel64 mode). Along these lines it was also wrong to base the displacement width decision solely on the operand size prefix: REX.W cancels this effect and hence needs taking into consideration, too. A disassembler change is needed here as well: XBEGIN was wrongly treated the same as direct CALL/JMP, which isn't the case - the operand size prefix does affect displacement size there, it's merely ignored when it comes to updating [ER]IP.
2019-12-27x86: consolidate Disp<NN> handling a littleJan Beulich4-121/+115
In memory operand addressing, which forms of displacement are permitted besides Disp8 is pretty clearly limited - outside of 64-bit mode, Disp16 or Disp32 only, depending on address size (MPX being special in not allowing Disp16), - in 64-bit mode, Disp32s or Disp64 without address size override, and solely Disp32 with one. Adjust assembler and i386-gen to match this, observing that templates already get adjusted before trying to match them against input depending on the presence of an address size prefix. This adjustment logic gets extended to all cases, as certain DispNN values should also be dropped when there's no such prefix. In fact behavior of the assembler, perhaps besides the exact diagnostics wording, should not differ between there being templates applicable to 64-bit and non-64-bit at the same time, or there being fully separate sets of templates, with their DispNN settings already reduced accordingly. This adjustment logic further gets guarded such that there wouldn't be and Disp<N> conversion based on address size prefix when this prefix doesn't control the width of the displacement (on branches other than absolute ones). These adjustments then also allow folding two MOV templates, which had been split between 64-bit and non-64-bits variants so far. Once in this area also - drop the bogus DispNN from JumpByte templates, leaving just the correct Disp8 there (compensated by i386_finalize_displacement() now setting Disp8 on their operands), - add the missing Disp32S to XBEGIN. Note that the changes make it necessary to temporarily mark a test as XFAIL; this will get taken care of by a subsequent patch. The failing parts are entirely bogus and will get replaced.
2019-12-26ubsan: crx: index 5 out of bounds for type 'operand_desc const[5]'Alan Modra2-1/+6
* crx-dis.c (get_number_of_operands): Don't access operands[] out of bounds.
2019-12-26ubsan: v850: left shift cannot be represented in type 'int'Alan Modra2-7/+12
Another 1 << 31 complaint. * v850-dis.c (disassemble): Avoid signed overflow. Don't use long vars when unsigned int will do.
2019-12-24ubsan: arm: shift exponent 32 is too large for 32-bit type 'unsigned int'Alan Modra2-3/+7
* arm-dis.c (print_insn_arm): Don't shift by 32 on unsigned int var.
2019-12-23ppc: misc minor build correctionsJan Beulich3-8/+14
Avoid shadowing a libiberty symbol (which oldish gcc warns about by default), and allow building cleanly on 32-bit distros.
2019-12-23ubsan: score: left shift of 2 by 31 places cannot be represented in type 'int'Alan Modra2-25/+28
* score-dis.c (print_insn_score32): Avoid signed overflow. (print_insn_score48): Likewise. Don't cast to int when printing hex values.
2019-12-23ubsan: iq2000: left shift of negative valueAlan Modra2-1/+5
cpu/ * iq2000.cpu (f-offset): Avoid left shift of negative values. opcodes/ * iq2000-ibld.c: Regenerate.
2019-12-23ubsan: d30v: left shift cannot be represented in type 'long long'Alan Modra2-17/+25
* d30v-dis.c (extract_value): Make num param a uint64_t, constify oper. Use unsigned vars. (print_insn): Make num var uint64_t. Constify oper and remove now unnecessary casts on extract_value calls. (print_insn_d30v): Use unsigned vars. Adjust printf formats.
2019-12-23ubsan: wasm: shift is too large for 64-bit type 'bfd_vma'Alan Modra2-11/+23
bfd/ * wasm-module.c (wasm_read_leb128): Don't allow oversize shifts. Catch value overflow. Sign extend only on terminating byte. opcodes/ * wasm32-dis.c (wasm_read_leb128): Don't allow oversize shifts. Catch value overflow. Sign extend only on terminating byte.
2019-12-20PR25281, sh disassembler abortAlan Modra2-6/+17
PR 25281 * sh-dis.c (print_insn_ddt): Properly check validity of MOVX_NOPY and MOVY_NOPX insns. For invalid cases include 0xf000 in the word printed. Print .word in more cases.
2019-12-20ubsan: or1k: left shift of negative valueAlan Modra2-2/+6
cpu/ * or1korbis.cpu (f-disp26, f-disp21): Don't left shift negative values. opcodes/ * or1k-ibld.c: Regenerate.
2019-12-20ubsan: hppa: left shift of negative valueAlan Modra2-8/+13
bfd/ * libhppa.h (hppa_field_adjust, bfd_hppa_insn2fmt): Delete forward declaration. Move ATTRIBUTE_UNUSED to definition. (sign_extend, low_sign_extend, sign_unext, low_sign_unext), (re_assemble_3, re_assemble_12, re_assemble_14, re_assemble_16), (re_assemble_17, re_assemble_21, re_assemble_22): Likewise. Make args and return value unsigned. Use unsigned variables. (hppa_rebuild_insn): Similarly. opcodes/ * hppa-dis.c (extract_16, extract_21, print_insn_hppa): Use unsigned variables.
2019-12-20ubsan: m68hc1x: left shift of negative valueAlan Modra2-105/+81
* m68hc11-dis.c (read_memory): Delete forward decls. (print_indexed_operand, print_insn): Likewise. (print_indexed_operand): Formatting. Don't rely on short being exactly 16 bits, make sign extension explicit. (print_insn): Likewise. Avoid signed overflow.
2019-12-19vax decoding of indexed addressing modeAlan Modra2-2/+16
This patch prevents print_insn_mode recursing into another index mode byte, which if repeated enough times will overflow private.the_buffer and scribble over other memory. * vax-dis.c (print_insn_mode): Stop index mode recursion.
2019-12-19PR25277, microblaze opcode enumeration vs ISO/IEC TS 18661-3:2015Dr N.W. Filardo3-4/+11
fadd, fmul, and fdiv are now, by ISO/IEC TS 18661-3:2015, defined to refer to functions from the runtime subsystem. PR 25277 * microblaze-opcm.h (enum microblaze_instr): Prefix fadd, fmul and fdiv with "mbi_". * microblaze-opc.h (opcodes): Adjust to suit.
2019-12-18More signed overflow fixesAlan Modra12-59/+70
The arc fix in create_map avoiding signed overflow by casting an unsigned char to unsigned int before shifting, shows one of the dangers of blinding doing that. The problem in this case was that the variable storing the value, newAuxRegister->address, was a long. Using the unsigned cast meant that the 32-bit value was zero extended when long is 64 bits. Previously we had a sign extension. Net result was that comparisons in arcExtMap_auxRegName didn't match. Of course, I could have cast the 32-bit unsigned value back to signed before storing in a long, but it's neater to just use an unsigned int for the address. opcodes/ * alpha-opc.c (OP): Avoid signed overflow. * arm-dis.c (print_insn): Likewise. * mcore-dis.c (print_insn_mcore): Likewise. * pj-dis.c (get_int): Likewise. * ppc-opc.c (EBD15, EBD15BI): Likewise. * score7-dis.c (s7_print_insn): Likewise. * tic30-dis.c (print_insn_tic30): Likewise. * v850-opc.c (insert_SELID): Likewise. * vax-dis.c (print_insn_vax): Likewise. * arc-ext.c (create_map): Likewise. (struct ExtAuxRegister): Make "address" field unsigned int. (arcExtMap_auxRegName): Pass unsigned address. (dump_ARC_extmap): Adjust. * arc-ext.h (arcExtMap_auxRegName): Update prototype.
2019-12-17ubsan: visium: left shift cannot be represented in type 'int'Alan Modra2-1/+5
* visium-dis.c (print_insn_visium): Avoid signed overflow.
2019-12-17ubsan: aarch64: left shift cannot be represented in type 'int64_t'Alan Modra3-13/+20
* aarch64-opc.c (value_fit_signed_field_p): Avoid signed overflow. (value_fit_unsigned_field_p): Likewise. (aarch64_wide_constant_p): Likewise. (operand_general_constraint_met_p): Likewise. * aarch64-opc.h (aarch64_wide_constant_p): Update prototype.
2019-12-17ubsan: nds32: left shift cannot be represented in type 'int'Alan Modra2-9/+15
Yet more. * nds32-dis.c (nds32_mask_opcode): Avoid signed overflow. (print_insn_nds32): Use uint64_t for "given" and "given1".
2019-12-17Remove tic80 supportAlan Modra10-1543/+12
This is one way of fixing ubsan bug reports, just delete the code. The assembler support was removed back in 2005 along with other non-BFD assemblers, but somehow the remainder of the port stayed in. bfd/ * coff-tic80.c: Delete file. * cpu-tic80.c: Delete file. * archures.c: Remove tic80 support. * coffcode.h: Likewise. * coffswap.h: Likewise. * targets.c: Likewise. * config.bfd: Likewise. * configure.ac: Likewise. * Makefile.am: Likewise. * Makefile.in: Regenerate. * bfd-in2.h: Regenerate. * configure: Regenerate. * po/SRC-POTFILES.in: Regenerate. binutils/ * testsuite/binutils-all/objcopy.exp: Remove tic80 support. * testsuite/binutils-all/objdump.exp: Likewise. gas/ * doc/as.texi: Remove mention of tic80. include/ * coff/tic80.h: Delete file. * opcode/tic80.h: Delete file. ld/ * emulparams/tic80coff.sh: Delete file. * scripttempl/tic80coff.sc: Delete file. * configure.tgt: Remove tic80 support. * Makefile.am: Likewise. * Makefile.in: Regenerate. * po/BLD-POTFILES.in: Regenerate. opcodes/ * tic80-dis.c: Delete file. * tic80-opc.c: Delete file. * disassemble.c: Remove tic80 support. * disassemble.h: Likewise. * Makefile.am: Likewise. * configure.ac: Likewise. * Makefile.in: Regenerate. * configure: Regenerate. * po/POTFILES.in: Regenerate.
2019-12-17ubsan: bpf: left shift cannot be represented in type 'DI' (aka 'long')Alan Modra2-1/+5
cpu/ * bpf.cpu (f-imm64): Avoid signed overflow. opcodes/ * bpf-ibld.c: Regenerate.
2019-12-16ubsan: aarch64: left shift of negative valueAlan Modra2-9/+12
* aarch64-dis.c (sign_extend): Return uint64_t. Rewrite without conditional. (aarch64_ext_imm): Avoid signed overflow.
2019-12-16ubsan: microblaze: left shift cannot be represented in type 'int'Alan Modra2-2/+8
* microblaze-dis.c (read_insn_microblaze): Avoid signed overflow.
2019-12-16ubsan: nios2: left shift cannot be represented in type 'int'Alan Modra2-2/+6
* nios2-dis.c (nios2_print_insn_arg): Avoid signed overflow
2019-12-16ubsan: xstormy16: left shift of negative valueAlan Modra2-1/+5
cpu/ * xstormy16.cpu (f-rel12a): Avoid signed overflow. opcodes/ * xstormy16-ibld.c: Regenerate.
2019-12-16asan: score: global-buffer-overflowAlan Modra2-9/+12
I'm flying blind here, not having an s+core s3 insn set reference, but this seems reasonably obvious from what is done by the assembler. s3_do16_rpop does some mixing of imm and reg values to place in the rpop reg field, but I'm not going to try to fix the disassembly there. * score-dis.c (print_insn_score16): Move rpush/rpop imm field value adjustment so that it doesn't affect reg field too.
2019-12-16ubsan: crx: left shift cannot be represented in type 'int'Alan Modra2-27/+21
The ubsan complaint is fixed by the SBM change, with similar possible complaints fixed by the EXTRACT change. The rest is just cleanup. include/ * opcode/crx.h (inst <match>): Make unsigned int. opcodes/ * crx-dis.c (EXTRACT, SBM): Avoid signed overflow. (get_number_of_operands, getargtype, getbits, getregname), (getcopregname, getprocregname, gettrapstring, getcinvstring), (getregliststring, get_word_at_PC, get_words_at_PC, build_mask), (powerof2, match_opcode, make_instruction, print_arguments), (print_arg): Delete forward declarations, moving static to.. (getregname, getcopregname, getregliststring): ..these definitions. (build_mask): Return unsigned int mask. (match_opcode): Use unsigned int vars.
2019-12-16ubsan: bfin: left shift of negative valueAlan Modra2-9/+12
* bfin-dis.c (fmtconst, fmtconst_val): Avoid signed overflow.
2019-12-16ubsan: nds32: left shift cannot be represented in type 'int'Alan Modra2-23/+15
Note that using 1u in N32_BIT makes all of N32_BIT, __MASK, __MF, __GF and __SEXT evaluate as unsigned int (the latter three when when their v arg is int or smaller). This would be a problem if assigning the result to a bfd_vma, long, or other type wider than an int since the __SEXT result would be zero extended to the wider type. Fortunately nds32 target code doesn't use wider types unnecessarily. include/ * opcode/nds32.h (N32_BIT): Define using 1u. (__SEXT): Use __MASK and N32_BIT. (N32_IMMS): Remove duplicate mask. opcodes/ * nds32-dis.c (print_insn16, print_insn32): Remove forward decls. (struct objdump_disasm_info): Delete. (nds32_parse_audio_ext, nds32_parse_opcode): Cast result of N32_IMMS to unsigned before shifting left.
2019-12-16ubsan: moxie: left shift of negative valueAlan Modra2-3/+7
Commit 8c9b4171877df didn't remove a glaring left shift of a number that had just been sign extended. * moxie-dis.c (INST2OFFSET): Don't left shift a signed value. (print_insn_moxie): Remove unnecessary cast.
2019-12-12csky: tidy csky_chars_to_numberAlan Modra2-4/+7
* csky-dis.c (csky_chars_to_number): Remove abort and unnecessary mask.
2019-12-11Remove more shifts for sign/zero extensionAlan Modra11-24/+35
cpu/ * epiphany.cpu (f-sdisp11): Don't sign extend with shifts. * lm32.cpu (f-branch, f-vall): Likewise. * m32.cpu (f-lab-8-16): Likewise. opcodes/ * arc-dis.c (BITS): Don't truncate high bits with shifts. * nios2-dis.c (nios2_print_insn_arg): Don't sign extend with shifts. * tic54x-dis.c (print_instruction): Likewise. * tilegx-opc.c (parse_insn_tilegx): Likewise. * tilepro-opc.c (parse_insn_tilepro): Likewise. * visium-dis.c (disassem_class0): Likewise. * pdp11-dis.c (sign_extend): Likewise. (SIGN_BITS): Delete. * epiphany-ibld.c: Regenerate. * lm32-ibld.c: Regenerate. * m32c-ibld.c: Regenerate.
2019-12-11Re: ubsan: ns32k: left shift cannot be represented in typeAlan Modra2-2/+6
* ns32k-dis.c (sign_extend): Correct last patch.
2019-12-11ubsan: vax: left shift cannot be represented in type 'int'Alan Modra2-1/+5
* vax-dis.c (NEXTLONG): Avoid signed overflow.
2019-12-11ubsan: v850: left shift cannot be represented in type 'long'Alan Modra2-4/+11
* v850-dis.c (get_operand_value): Use unsigned arithmetic. Don't sign extend using shifts.
2019-12-11ubsan: tic6x: shift left of intAlan Modra2-2/+6
* tic6x-dis.c (tic6x_extract_32): Avoid signed overflow.
2019-12-11ubsan: tic4x: segv and signed shiftsAlan Modra2-7/+15
* tic4x-dis.c (tic4x_print_register): Formatting. Don't segfault on NULL registertable entry. (tic4x_hash_opcode): Use unsigned arithmetic.
2019-12-11ubsan: s12z: left shift cannot be represented in type 'int'Alan Modra2-3/+5
* s12z-opc.c (z_decode_signed_value): Avoid signed overflow.
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