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authorAlan Modra <amodra@gmail.com>2019-12-16 10:00:39 +1030
committerAlan Modra <amodra@gmail.com>2019-12-16 17:34:29 +1030
commit84e098cdea4eb6a5ddc525a2145ffe66475fa2af (patch)
tree569550d423ddb6dd4ebaaeadf3e2ae77478b726f /opcodes
parent36bd8ea7f06126d3e73d9644325c4bbfbd5c89f4 (diff)
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asan: score: global-buffer-overflow
I'm flying blind here, not having an s+core s3 insn set reference, but this seems reasonably obvious from what is done by the assembler. s3_do16_rpop does some mixing of imm and reg values to place in the rpop reg field, but I'm not going to try to fix the disassembly there. * score-dis.c (print_insn_score16): Move rpush/rpop imm field value adjustment so that it doesn't affect reg field too.
Diffstat (limited to 'opcodes')
-rw-r--r--opcodes/ChangeLog5
-rw-r--r--opcodes/score-dis.c16
2 files changed, 12 insertions, 9 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog
index 9cc0ba4..ce56ec0 100644
--- a/opcodes/ChangeLog
+++ b/opcodes/ChangeLog
@@ -1,5 +1,10 @@
2019-12-16 Alan Modra <amodra@gmail.com>
+ * score-dis.c (print_insn_score16): Move rpush/rpop imm field
+ value adjustment so that it doesn't affect reg field too.
+
+2019-12-16 Alan Modra <amodra@gmail.com>
+
* crx-dis.c (EXTRACT, SBM): Avoid signed overflow.
(get_number_of_operands, getargtype, getbits, getregname),
(getcopregname, getprocregname, gettrapstring, getcinvstring),
diff --git a/opcodes/score-dis.c b/opcodes/score-dis.c
index 69c801b..74a1f1d 100644
--- a/opcodes/score-dis.c
+++ b/opcodes/score-dis.c
@@ -954,15 +954,6 @@ print_insn_score16 (bfd_vma pc, struct disassemble_info *info, long given)
reg = given >> bitstart;
reg &= (2 << (bitend - bitstart)) - 1;
- /* Check rpush rd, 0 and rpop! rd, 0.
- If reg = 0, then set to 32. */
- if (((given & 0x00007c00) == 0x00006c00
- || (given & 0x00007c00) == 0x00006800)
- && reg == 0)
- {
- reg = 32;
- }
-
switch (*c)
{
case 'R':
@@ -972,6 +963,13 @@ print_insn_score16 (bfd_vma pc, struct disassemble_info *info, long given)
func (stream, "%s", score_regnames[reg]);
break;
case 'd':
+ /* Check rpush rd, 0 and rpop! rd, 0.
+ If 0, then print 32. */
+ if (((given & 0x00007c00) == 0x00006c00
+ || (given & 0x00007c00) == 0x00006800)
+ && reg == 0)
+ reg = 32;
+
if (*(c + 1) == '\0')
func (stream, "%ld", reg);
else