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| author | Jan Beulich <jbeulich@suse.com> | 2020-01-03 10:16:44 +0100 |
|---|---|---|
| committer | Jan Beulich <jbeulich@suse.com> | 2020-01-03 10:16:44 +0100 |
| commit | 5437a02abc9fe106054965828787e8f232692935 (patch) | |
| tree | 4723e3eddeef436e20d15d44c109b0f1529db3ba /opcodes | |
| parent | 567dfba2bed4bce68a13b0c8963dec9605dea6c8 (diff) | |
| download | gdb-5437a02abc9fe106054965828787e8f232692935.zip gdb-5437a02abc9fe106054965828787e8f232692935.tar.gz gdb-5437a02abc9fe106054965828787e8f232692935.tar.bz2 | |
Arm64: correct address index operands for LD1RO{H,W,D}
Just like their LD1RQ{H,W,D} counterparts, as per the specification the
index registers get scaled by element size.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 11 | ||||
| -rw-r--r-- | opcodes/aarch64-tbl.h | 8 |
2 files changed, 12 insertions, 7 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 19a7b3f..fb9f9e0 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,17 +1,22 @@ 2020-01-03 Jan Beulich <jbeulich@suse.com> - * opcodes/aarch64-tbl.h (aarch64_opcode_table): Correct SIMD + * aarch64-tbl.h (aarch64_opcode_table): Use + SVE_ADDR_RX_LSL{1,2,3} for LD1RO{H,W,D}. + +2020-01-03 Jan Beulich <jbeulich@suse.com> + + * aarch64-tbl.h (aarch64_opcode_table): Correct SIMD forms of SUDOT and USDOT. 2020-01-03 Jan Beulich <jbeulich@suse.com> - * opcodes/aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from + * aarch64-tbl.h (aarch64_opcode_table): Drop 'i' from uzip{1,2}. * opcodes/aarch64-dis-2.c: Re-generate. 2020-01-03 Jan Beulich <jbeulich@suse.com> - * opcodes/aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit + * aarch64-tbl.h (aarch64_opcode_table): Correct 64-bit FMMLA encoding. * opcodes/aarch64-dis-2.c: Re-generate. diff --git a/opcodes/aarch64-tbl.h b/opcodes/aarch64-tbl.h index 2655ca5..48872e4 100644 --- a/opcodes/aarch64-tbl.h +++ b/opcodes/aarch64-tbl.h @@ -5074,10 +5074,10 @@ struct aarch64_opcode aarch64_opcode_table[] = INT8MATMUL_SVE_INSNC ("sudot", 0x44a01c00, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm3_INDEX), OP_SVE_SBB, 0, C_SCAN_MOVPRFX, 0), F32MATMUL_SVE_INSNC ("fmmla", 0x64a0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_S, 0, C_SCAN_MOVPRFX, 0), F64MATMUL_SVE_INSNC ("fmmla", 0x64e0e400, 0xffe0fc00, sve_misc, OP3 (SVE_Zd, SVE_Zn, SVE_Zm_16), OP_SVE_VVV_D, 0, C_SCAN_MOVPRFX, 0), - F64MATMUL_SVE_INSN ("ld1rob", 0xa4200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0), - F64MATMUL_SVE_INSN ("ld1roh", 0xa4a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_HZU, F_OD(1), 0), - F64MATMUL_SVE_INSN ("ld1row", 0xa5200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_SZU, F_OD(1), 0), - F64MATMUL_SVE_INSN ("ld1rod", 0xa5a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_DZU, F_OD(1), 0), + F64MATMUL_SVE_INSN ("ld1rob", 0xa4200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX), OP_SVE_BZU, F_OD(1), 0), + F64MATMUL_SVE_INSN ("ld1roh", 0xa4a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL1), OP_SVE_HZU, F_OD(1), 0), + F64MATMUL_SVE_INSN ("ld1row", 0xa5200000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL2), OP_SVE_SZU, F_OD(1), 0), + F64MATMUL_SVE_INSN ("ld1rod", 0xa5a00000, 0xffe0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RX_LSL3), OP_SVE_DZU, F_OD(1), 0), F64MATMUL_SVE_INSN ("ld1rob", 0xa4202000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_BZU, F_OD(1), 0), F64MATMUL_SVE_INSN ("ld1roh", 0xa4a02000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_HZU, F_OD(1), 0), F64MATMUL_SVE_INSN ("ld1row", 0xa5202000, 0xfff0e000, sve_misc, OP3 (SVE_ZtxN, SVE_Pg3, SVE_ADDR_RI_S4x32), OP_SVE_SZU, F_OD(1), 0), |