aboutsummaryrefslogtreecommitdiff
path: root/opcodes
AgeCommit message (Expand)AuthorFilesLines
2019-04-07print_insn_powerpc tidyAlan Modra2-26/+29
2019-04-07PR24421, Wrong brackets in opcodes/arm-dis.cAlan Modra2-213/+219
2019-04-05x86: Support Intel AVX512 BF16Xuepeng Guo8-4133/+4576
2019-04-05PowerPC bc extended branch mnemonics and "y" hintsAlan Modra2-141/+148
2019-04-05PowerPC disassembler: Don't emit trailing spacesAlan Modra2-4/+16
2019-04-04Add extended mnemonics for bctar. Fix setting of 'at' branch hints.Peter Bergner2-49/+298
2019-03-28PR24390, Don't decode mtfsb field as a cr fieldAlan Modra3-6/+20
2019-03-25Arm: Fix Arm disassembler mapping symbol search.Tamar Christina2-148/+107
2019-03-25AArch64: Have -D override mapping symbol as documented.Tamar Christina2-1/+7
2019-03-25AArch64: Fix AArch64 disassembler mapping symbol searchTamar Christina2-6/+43
2019-03-25AArch64: Fix disassembler bug with out-of-order sectionsTamar Christina2-1/+11
2019-03-19ix86: Disable AVX512F when disabling AVX2H.J. Lu3-7/+14
2019-03-18x86: Optimize EVEX vector load/store instructionsH.J. Lu3-12/+19
2019-03-12Add missing changelogs for previous commits.Andreas Krebbel1-0/+9
2019-03-12S/390: arch13: Adjust to recent changesAndreas Krebbel1-5/+5
2019-03-12S/390: arch13: Add instruction descriptionsAndreas Krebbel1-101/+115
2019-02-08Add missing ChangeLog files for previous patch.Jim Wilson1-0/+5
2019-02-08RISC-V: Compress 3-operand beq/bne against x0.Jim Wilson1-0/+2
2019-02-07Arm: Backport hlt to all architectures.Tamar Christina2-1/+6
2019-02-07AArch64: Add verifier for By elem Single and Double sized instructions.Tamar Christina4-9/+46
2019-02-07Updated Swedish translation for the opcodes sub-directoryNick Clifton2-308/+352
2019-01-31S/390: Implement instruction set extensionsAndreas Krebbel4-0/+117
2019-01-25AArch64: Add missing changelog for Update encodings for stg, st2g, stzg and s...Tamar Christina1-0/+9
2019-01-25AArch64: Update encodings for stg, st2g, stzg and st2zg.Sudi Das1-10/+10
2019-01-25AArch64: Add new STZGM instruction for Armv8.5-A Memory Tagging Extension.Sudi Das5-1580/+1599
2019-01-25AArch64: Remove ldgv and stgv instructions from Armv8.5-A Memory Tagging Exte...Sudi Das10-1709/+1658
2019-01-23Updated translations for some of the binutils subdirectory.Nick Clifton2-305/+351
2019-01-21Updated translations for various binutils subdirectories.Nick Clifton3-609/+696
2019-01-20[MIPS] fix typo in mips_arch_choices.Chenghua Xu2-3/+7
2019-01-19Change version to 2.32.51 and regenerate configure and pot files.Nick Clifton3-263/+304
2019-01-19Add markers for 2.32 branch to NEWS and ChangeLog files.Nick Clifton1-0/+4
2019-01-13Add RXv3 instructions.Yoshinori Sato3-1569/+5442
2019-01-09S12Z: Don't crash when disassembling invalid instructions.John Darrington2-3/+5
2019-01-09S12Z: Fix disassembly of indexed OPR operands with zero index.John Darrington2-30/+32
2019-01-09Adjust bfd/warning.m4 egrep patternsAndrew Paprocki2-5/+9
2019-01-07s12z regenAlan Modra3-3/+9
2019-01-03S12Z: opcodes: Separate the decoding of operations from their display.John Darrington8-2548/+3241
2019-01-01Update year range in copyright notice of binutils filesAlan Modra269-272/+276
2019-01-01ChangeLog rotationAlan Modra2-2538/+2552
2018-12-28PR24028, PPC_INT_FMTAlan Modra2-10/+16
2018-12-18Include bfd_stdint.h in bfd.hAlan Modra8-6/+17
2018-12-07RISC-V: Fix 4-arg add parsing.Jim Wilson2-1/+6
2018-12-06sim/opcodes: Allow use of out of tree cgen source directoryAndrew Burgess3-8/+26
2018-12-06opcodes/riscv: Hide '.L0 ' fake symbolsAndrew Burgess3-0/+28
2018-12-03RISC-V: Accept version, supervisor ext and more than one NSE for -march.Jim Wilson2-1/+6
2018-12-03[aarch64] - Only use MOV for disassembly when shifter op is LSL #0Egeyar Bagcioglu2-1/+8
2018-11-29RISC-V: Add missing c.unimp instruction.Jim Wilson2-1/+7
2018-11-27RISC-V: Add .insn CA support.Jim Wilson2-2/+12
2018-11-21S12Z opcodes: Fix bug disassembling certain shift instructions.John Darrington2-19/+30
2018-11-13opcodes/nfp: Fix disassembly of crc[] with swapped operands.Francois H. Theron2-6/+10
generated by cgit v1.1 at 2024-11-22 09:08:04 +0000