Age | Commit message (Expand) | Author | Files | Lines |
2024-01-11 | LoongArch: Discard extra spaces in objdump output | Lulu Cai | 1 | -1/+6 |
2024-01-10 | gas: aarch64: Add system registers for Debug and PMU extensions | Saurabh Jha | 1 | -0/+41 |
2024-01-09 | x86: add missing APX logic to cpu_flags_match() | Jan Beulich | 1 | -1/+7 |
2024-01-09 | aarch64: ADD FEAT_THE RCWCAS instructions. | Srinath Parvathaneni | 2 | -139/+961 |
2024-01-09 | aarch64: Regenerate aarch64-*-2.c files | Victor Do Nascimento | 3 | -2407/+2454 |
2024-01-09 | aarch64: Add support for 128-bit system register mrrs and msrr insns | Victor Do Nascimento | 3 | -1/+12 |
2024-01-09 | aarch64: Add xs variants of tlbip operands | Victor Do Nascimento | 2 | -0/+125 |
2024-01-09 | aarch64: Implement TLBIP 128-bit instruction | Victor Do Nascimento | 1 | -0/+3 |
2024-01-09 | aarch64: Create QL_SRC_X2 and QL_DEST_X2 qualifier macros | Victor Do Nascimento | 1 | -0/+12 |
2024-01-09 | aarch64: Apply narrowing of allowed immediate values for SYSP | Victor Do Nascimento | 1 | -1/+1 |
2024-01-09 | aarch64: Add support for the SYSP 128-bit system instruction | Victor Do Nascimento | 3 | -3/+11 |
2024-01-09 | aarch64: Add support for xzr register in register pair operands | Victor Do Nascimento | 3 | -4/+24 |
2024-01-09 | aarch64: Expand maximum number of operands from 5 to 6 | Victor Do Nascimento | 1 | -0/+2 |
2024-01-09 | aarch64: Add +d128 architectural feature support | Victor Do Nascimento | 1 | -0/+5 |
2024-01-08 | aarch64: Add ite feature system registers. | srinath | 1 | -0/+4 |
2024-01-07 | i386: Correct adcx suffix in disassembler | H.J. Lu | 1 | -4/+13 |
2024-01-05 | Add AMD znver5 processor support | Tejas Joshi | 2 | -0/+12 |
2024-01-05 | x86: corrections to CPU attribute/flags splitting | Jan Beulich | 1 | -1/+10 |
2024-01-05 | RISC-V: T-HEAD: Fix wrong instruction encoding for th.vsetvli | Jin Ma | 2 | -1/+35 |
2024-01-04 | Update year range in copyright notice of binutils files | Alan Modra | 275 | -336/+340 |
2024-01-04 | LoongArch: Fix some macro that cannot be expanded properly | Lulu Cai | 1 | -12/+12 |
2023-12-30 | LoongArch: Commas inside double quotes | Alan Modra | 1 | -1/+5 |
2023-12-29 | LoongArch: opcodes: Add support for tls le relax. | changjiachen | 1 | -0/+1 |
2023-12-29 | RISC-V: THEAD: Add 5 assembly pseudoinstructions for XTheadVector extension | Jin Ma | 1 | -0/+5 |
2023-12-28 | Support APX JMPABS for disassembler | Hu, Lin1 | 1 | -2/+35 |
2023-12-28 | Support APX pushp/popp | Cui, Lili | 5 | -1061/+1101 |
2023-12-28 | Support APX Push2/Pop2 | Mo, Zewei | 7 | -1960/+2064 |
2023-12-28 | Support APX NDD | konglin1 | 6 | -413/+1650 |
2023-12-28 | Support APX GPR32 with extend evex prefix | Cui, Lili | 8 | -4182/+4772 |
2023-12-28 | Created an empty EVEX_MAP4_ sub-table for EVEX instructions. | Cui, Lili | 2 | -0/+292 |
2023-12-28 | Support APX GPR32 with rex2 prefix | Cui, Lili | 8 | -11743/+12227 |
2023-12-25 | LoongArch: Add new relocs and macro for TLSDESC. | Lulu Cai | 1 | -0/+54 |
2023-12-25 | Re: LoongArch: Add support for <b ".L1"> and <beq, $t0, $t1, ".L1"> | Alan Modra | 1 | -14/+16 |
2023-12-20 | s390: Add suffix to conditional branch instruction descriptions | Jens Remus | 1 | -34/+44 |
2023-12-20 | s390: Optionally print instruction description in disassembly | Jens Remus | 3 | -39/+55 |
2023-12-20 | s390: Use safe string functions and length macros in s390-mkopc | Jens Remus | 1 | -25/+52 |
2023-12-20 | s390: Enhance error handling in s390-mkopc | Jens Remus | 1 | -14/+35 |
2023-12-20 | s390: Provide IBM z16 (arch14) instruction descriptions | Jens Remus | 1 | -28/+38 |
2023-12-20 | s390: Align letter case of instruction descriptions | Jens Remus | 1 | -21/+21 |
2023-12-20 | s390: Fix build when using EXEEXT_FOR_BUILD | Jens Remus | 2 | -4/+10 |
2023-12-19 | aarch64: Add FEAT_ITE support | Andrea Corallo | 3 | -2/+12 |
2023-12-19 | aarch64: Add FEAT_ECBHB support | Andrea Corallo | 3 | -1/+7 |
2023-12-19 | aarch64: Add FEAT_SPECRES2 support | Andrea Corallo | 4 | -2074/+2083 |
2023-12-19 | x86: Remove the restriction for size of the mask register in AVX10 | Haochen Jiang | 4 | -3777/+3762 |
2023-12-18 | LoongArch: Add call36 and tail36 pseudo instructions for medium code model | mengqinggang | 1 | -0/+11 |
2023-12-15 | revert "x86: allow 32-bit reg to be used with U{RD,WR}MSR" | Jan Beulich | 2 | -4/+4 |
2023-12-15 | x86: fold assembly dialect attributes | Jan Beulich | 4 | -7498/+3755 |
2023-12-15 | x86: Intel syntax implies Intel mnemonics | Jan Beulich | 3 | -333/+298 |
2023-12-14 | RISC-V: Fix the wrong encoding and operand of the XTheadFmv extension. | Jin Ma | 1 | -1/+1 |
2023-12-14 | Remove redundant Byte, Word, Dword and Qword from insn templates. | Cui, Lili | 1 | -123/+123 |