| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2024-11-20 | PowerPC: Add support for RFC02677 - VSX Vector Rotate Left Word | Peter Bergner | 1 | -0/+1 |
| 2024-11-20 | arm: Support pac_key_* register operand for MRS/MSR in Armv8.1-M Mainline | Andre Vieira | 1 | -4/+27 |
| 2024-11-20 | RISC-V: Add Zcmt instructions and csr. | Jiawei | 2 | -0/+28 |
| 2024-11-19 | Support x86 Intel MSR_IMM | Hu, Lin1 | 6 | -833/+914 |
| 2024-11-18 | x86: rename SPACE_{,E}VEX_MAP<N> | Jan Beulich | 4 | -744/+744 |
| 2024-11-18 | x86: VP2INTERSECT{D,Q} have mask register destination group | Jan Beulich | 2 | -3/+3 |
| 2024-11-18 | x86: generalize "implicit quad group" handling | Jan Beulich | 2 | -10/+12 |
| 2024-11-18 | s390: Add arch15 Concurrent-Functions Facility insns | Jens Remus | 2 | -0/+10 |
| 2024-11-18 | s390: Add arch15 instruction names | Jens Remus | 1 | -106/+114 |
| 2024-11-18 | opcodes: fix -std=gnu23 compatibility wrt static_assert | Sam James | 3 | -3/+7 |
| 2024-11-08 | aarch64: add flag OPD_F_UNSIGNED to distinguish signedness of immediate operands | Matthieu Longo | 2 | -23/+77 |
| 2024-11-08 | aarch64: improve debuggability on array of enum | Matthieu Longo | 1 | -3/+3 |
| 2024-11-08 | aarch64: change returned type to bool to match semantic of functions | Matthieu Longo | 2 | -172/+172 |
| 2024-11-08 | arm, objdump: print obsolote warning when 26-bit set in instructions | Andre Vieira | 1 | -25/+19 |
| 2024-11-08 | arm, objdump: Make objdump use bfd's machine detection to drive disassembly | Andre Vieira | 1 | -4/+23 |
| 2024-10-31 | RISC-V: Dump instruction without checking architecture support as usual. | Nelson Chu | 1 | -1/+7 |
| 2024-10-30 | x86/APX: support JMPABS also in assembler | Jan Beulich | 3 | -903/+924 |
| 2024-10-29 | x86: use <xyz> for VFPCLASSP{S,D} | Jan Beulich | 2 | -35/+31 |
| 2024-10-18 | x86: Regenerate missing table files | MayShao-oc | 3 | -4388/+4428 |
| 2024-10-18 | x86: Support x86 ZHAOXIN GMI instructions | MayShao-oc | 4 | -1/+56 |
| 2024-10-16 | Support Intel AVX10.2 convert instructions | Liwei Xu | 6 | -1996/+2488 |
| 2024-10-14 | x86: also template-expand trailing mnemonic part | Jan Beulich | 1 | -60/+72 |
| 2024-10-14 | LoongArch: Fixed R_LARCH_[32/64]_PCREL generation bug | Lulu Cai | 1 | -1/+2 |
| 2024-10-11 | Support Intel AVX10.2 media instructions | Haochen Jiang | 7 | -702/+893 |
| 2024-10-10 | s390: Add arch15 instructions | Andreas Krebbel | 3 | -3/+127 |
| 2024-10-07 | m68k: Support for jump visualization in disassembly | Andreas Schwab | 1 | -0/+27 |
| 2024-09-27 | RISC-V: correct alignment directive handling for text sections | Jan Beulich | 1 | -1/+1 |
| 2024-09-27 | x86: optimize {,V}INSERTPS with certain immediates | Jan Beulich | 2 | -7/+7 |
| 2024-09-27 | x86: optimize {,V}EXTRACT{F,I}{128,32x{4,8},64x{2,4}} with immediate 0 | Jan Beulich | 2 | -20/+20 |
| 2024-09-27 | x86: optimize {,V}EXTRACTPS with immediate 0 | Jan Beulich | 2 | -12/+12 |
| 2024-09-26 | x86: templatize SIMD narrowing-move templates | Jan Beulich | 2 | -72/+32 |
| 2024-09-26 | x86: templatize SIMD sign-/zero-extension templates | Jan Beulich | 2 | -251/+220 |
| 2024-09-26 | x86: templatize SIMD FP binary-logic templates | Jan Beulich | 2 | -282/+271 |
| 2024-09-26 | x86: further templatize FMA templates | Jan Beulich | 2 | -349/+339 |
| 2024-09-26 | x86: templatize SIMD FP arithmetic templates | Jan Beulich | 2 | -1135/+1100 |
| 2024-09-18 | x86/APX: Don't promote AVX/AVX2 instructions out of APX spec | H.J. Lu | 2 | -337/+197 |
| 2024-09-12 | s390: Relax risbg[n]z, risb{h|l}gz, {rns|ros|rxs}bgt operand constraints | Jens Remus | 1 | -15/+9 |
| 2024-09-12 | s390: Simplify (dis)assembly of insn operands with const bits | Jens Remus | 2 | -23/+17 |
| 2024-09-11 | x86/APX: correct disassembly for EVEX.B4 | Jan Beulich | 1 | -2/+3 |
| 2024-09-09 | s390: Align opcodes to lower-case | Jens Remus | 1 | -1/+1 |
| 2024-09-06 | x86/APX: use D for 2-operand CFCMOVcc | Jan Beulich | 2 | -577/+276 |
| 2024-09-06 | x86/APX: optimize certain reg-only CFCMOVcc forms | Jan Beulich | 2 | -31/+31 |
| 2024-09-06 | x86: templatize VNNI templates | Jan Beulich | 2 | -46/+37 |
| 2024-09-03 | RISC-V: Add support for XCVsimd extension in CV32E40P | Mary Bennett | 2 | -0/+231 |
| 2024-09-02 | Support ymm rounding control for Intel AVX10.2 | Haochen Jiang | 6 | -629/+666 |
| 2024-08-30 | x86/APX: drop %SW disassembler macro again | Jan Beulich | 2 | -17/+19 |
| 2024-08-30 | x86: limit RegRex64 use | Jan Beulich | 2 | -48/+48 |
| 2024-08-27 | RISC-V: PR32036, Support Zcmp cm.mva01s and cm.mvsa01 instructions. | Jiawei | 2 | -0/+28 |
| 2024-08-16 | opcodes/cgen: drop trailing whitespace also for cris | Jan Beulich | 2 | -48/+48 |
| 2024-08-12 | Revert "gas: have scrubber retain more whitespace" | H.J. Lu | 14 | -447/+234 |
