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2018-07-12This patch adds support for the SSBB and PSSBB speculation barrier instructio...Nick Clifton5-1006/+1024
2018-07-12Add remainder of Em16 restrictions for AArch64 gas.Tamar Christina2-26/+34
2018-07-11Adds the speculation barrier instructions to the ARM assembler and disassembler.Sudakshina Das2-6/+16
2018-07-11x86: adjust monitor/mwait templatesJan Beulich3-57/+67
2018-07-11x86: drop {,reg16_}inoutportreg variablesJan Beulich3-14/+7
2018-07-11x86/Intel: accept memory operand size specifiers for CET insnsJan Beulich3-8/+14
2018-07-11x86: replace off-by-one OTMaxJan Beulich2-4/+10
2018-07-09S12Z/opcodes: Correct a `reg' global shadowing error for pre-4.8 GCCMaciej W. Rozycki2-14/+22
2018-07-06Fix SBO bit in disassembly mask for ldrah on AArch64.Tamar Christina2-1/+6
2018-07-06Fix the read/write flag for these registers on AArch64Tamar Christina2-5/+11
2018-07-02GDB PR tdep/8282: MIPS: Wire in `set disassembler-options'Maciej W. Rozycki5-68/+205
2018-07-02[ARM] Update bfd's Tag_CPU_arch knowledgeThomas Preud'homme2-21/+58
2018-06-29Fix AArch64 encodings for by element instructions.Tamar Christina7-165/+194
2018-06-26Updated translations.Nick Clifton4-865/+1945
2018-06-26Fix spelling mistakes.Nick Clifton2-1/+5
2018-06-24Regenerate configure and pot files with updated binutils version number.Nick Clifton3-97/+140
2018-06-24Add 2.30 branch notes to ChangeLogs and NEWS files.Nick Clifton1-0/+4
2018-06-22Correct negs aliasing on AArch64.Tamar Christina4-5/+11
2018-06-21MIPS/opcodes: Fix a typo in `-M ginv' option descriptionMaciej W. Rozycki2-1/+6
2018-06-20RISC-V: Accept constant operands in la and llaSebastian Huber2-2/+8
2018-06-19Bump to autoconf 2.69 and automake 1.15.1Simon Marchi6-995/+1563
2018-06-14MIPS: Add Global INValidate ASE supportFaraz Shahbazker3-2/+30
2018-06-13MIPS: Add CRC ASE supportScott Egerton3-2/+26
2018-06-08Prevent undefined FMOV instructions being accepted by the AArch64 assembler.Egeyar Bagcioglu2-2/+22
2018-06-06Fix xtensa "clobbered by longjmp" warningsAlan Modra2-6/+12
2018-06-04xtensa: use property tables for correct disassemblyMax Filippov2-22/+206
2018-06-01Bump version number to 2.30.52H.J. Lu2-10/+14
2018-06-01x86: fold MOV to/from segment register templatesJan Beulich3-119/+16
2018-06-01x86: don't emit REX.W for SLDT and STRJan Beulich3-4/+9
2018-06-01x86/Intel: accept "oword ptr" for INVPCIDJan Beulich3-6/+11
2018-06-01Make _bfd_error_handler available outside libbfdAlan Modra6-5/+12
2018-05-30Add znver2 support.Amit Pawar3-0/+15
2018-05-25s12z regenAlan Modra3-1/+7
2018-05-21Remove fake operand handling for extended mnemonics.Peter Bergner3-102/+123
2018-05-18Add support for the Freescale s12z processor.John Darrington9-0/+2765
2018-05-18opcodes sources should not include libbfd.hAlan Modra2-7/+10
2018-05-17Updated simplified Chinese translation for the opcodes directory.Nick Clifton2-466/+465
2018-05-16Fix disassembly mask for vector sdot on AArch64.Tamar Christina3-160/+186
2018-05-15Implement Read/Write constraints on system registers on AArch64Tamar Christina6-94/+197
2018-05-15Allow non-fatal errors to be emitted and for disassembly notes be placed on A...Tamar Christina3-3/+35
2018-05-15Modify AArch64 Assembly and disassembly functions to be able to fail and repo...Tamar Christina9-556/+759
2018-05-15Fix error messages in the NFP sources when building for 32-bit targets.Francois H. Theron2-45/+44
2018-05-09x86: Remove Disp<N> from movidir{i,64b}H.J. Lu2-3/+7
2018-05-09PR22069, Several instances of register accidentally spelled as regsiterAlan Modra3-2/+7
2018-05-08RISC-V: Add missing hint instructions from RV128I.Jim Wilson2-9/+54
2018-05-08Correct powerpc spe opcode lookupAlan Modra2-6/+12
2018-05-07Simplify VLE handling in print_insn_powerpc().Peter Bergner2-35/+26
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu7-5115/+5285
2018-05-07x86: Replace AddrPrefixOp0 with AddrPrefixOpRegH.J. Lu4-14/+23
2018-05-07Cleanup ppc code dealing with opcode dumps.Peter Bergner3-44/+39
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