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| author | Tamar Christina <tamar.christina@arm.com> | 2018-07-06 16:15:41 +0100 |
|---|---|---|
| committer | Tamar Christina <tamar.christina@arm.com> | 2018-07-06 16:17:17 +0100 |
| commit | cba05feb51cb97f75f9a7814b081ce45245ac7b2 (patch) | |
| tree | 509612430e3ddb3c38ed28cb928229c761182757 /opcodes | |
| parent | e0e5e971ae89da1ded13013bb7378dc5f09363af (diff) | |
| download | gdb-cba05feb51cb97f75f9a7814b081ce45245ac7b2.zip gdb-cba05feb51cb97f75f9a7814b081ce45245ac7b2.tar.gz gdb-cba05feb51cb97f75f9a7814b081ce45245ac7b2.tar.bz2 | |
Fix the read/write flag for these registers on AArch64
The previous constraints were based on information already in opcodes and it
seems that a few of them were wrong. I have now hand verified the ones changed
by the previous patch and corrected where needed.
This prevents a warning to be issued when one shouldn't be.
opcodes/
PR binutils/23369
* aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1,
vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1.
gas/testsuite/
PR binutils/23369
* gas/aarch64/msr.d (csselr_el1,
vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1): New.
* gas/aarch64/msr.s: Likewise.
Diffstat (limited to 'opcodes')
| -rw-r--r-- | opcodes/ChangeLog | 6 | ||||
| -rw-r--r-- | opcodes/aarch64-opc.c | 10 |
2 files changed, 11 insertions, 5 deletions
diff --git a/opcodes/ChangeLog b/opcodes/ChangeLog index 149737e..70d35eb 100644 --- a/opcodes/ChangeLog +++ b/opcodes/ChangeLog @@ -1,3 +1,9 @@ +2018-07-06 Tamar Christina <tamar.christina@arm.com> + + PR binutils/23369 + * aarch64-opc.c (aarch64_sys_regs): Make read/write csselr_el1, + vsesr_el2, osdtrrx_el1, osdtrtx_el1, pmsidr_el1. + 2018-07-02 Maciej W. Rozycki <macro@mips.com> PR tdep/8282 diff --git a/opcodes/aarch64-opc.c b/opcodes/aarch64-opc.c index 2a10f00..ba2af7b 100644 --- a/opcodes/aarch64-opc.c +++ b/opcodes/aarch64-opc.c @@ -3735,7 +3735,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = { "id_aa64afr1_el1", CPENC(3,0,C0,C5,5), F_REG_READ }, /* RO */ { "id_aa64zfr0_el1", CPENC (3, 0, C0, C4, 4), F_ARCHEXT | F_REG_READ }, /* RO */ { "clidr_el1", CPENC(3,1,C0,C0,1), F_REG_READ }, /* RO */ - { "csselr_el1", CPENC(3,2,C0,C0,0), F_REG_READ }, /* RO */ + { "csselr_el1", CPENC(3,2,C0,C0,0), 0 }, { "vpidr_el2", CPENC(3,4,C0,C0,0), 0 }, { "vmpidr_el2", CPENC(3,4,C0,C0,5), 0 }, { "sctlr_el1", CPENC(3,0,C1,C0,0), 0 }, @@ -3795,7 +3795,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = { "esr_el2", CPENC(3,4,C5,C2,0), 0 }, { "esr_el3", CPENC(3,6,C5,C2,0), 0 }, { "esr_el12", CPENC (3, 5, C5, C2, 0), F_ARCHEXT }, - { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT | F_REG_READ }, /* RO */ + { "vsesr_el2", CPENC (3, 4, C5, C2, 3), F_ARCHEXT }, { "fpexc32_el2", CPENC(3,4,C5,C3,0), 0 }, { "erridr_el1", CPENC (3, 0, C5, C3, 0), F_ARCHEXT | F_REG_READ }, /* RO */ { "errselr_el1", CPENC (3, 0, C5, C3, 1), F_ARCHEXT }, @@ -3879,8 +3879,8 @@ const aarch64_sys_reg aarch64_sys_regs [] = { "dbgdtr_el0", CPENC(2,3,C0, C4, 0), 0 }, { "dbgdtrrx_el0", CPENC(2,3,C0, C5, 0), F_REG_READ }, /* r */ { "dbgdtrtx_el0", CPENC(2,3,C0, C5, 0), F_REG_WRITE }, /* w */ - { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), F_REG_READ }, /* r */ - { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), F_REG_WRITE }, /* w */ + { "osdtrrx_el1", CPENC(2,0,C0, C0, 2), 0 }, + { "osdtrtx_el1", CPENC(2,0,C0, C3, 2), 0 }, { "oseccr_el1", CPENC(2,0,C0, C6, 2), 0 }, { "dbgvcr32_el2", CPENC(2,4,C0, C7, 0), 0 }, { "dbgbvr0_el1", CPENC(2,0,C0, C0, 4), 0 }, @@ -3965,7 +3965,7 @@ const aarch64_sys_reg aarch64_sys_regs [] = { "pmsfcr_el1", CPENC (3, 0, C9, C9, 4), F_ARCHEXT }, /* rw */ { "pmsevfr_el1", CPENC (3, 0, C9, C9, 5), F_ARCHEXT }, /* rw */ { "pmslatfr_el1", CPENC (3, 0, C9, C9, 6), F_ARCHEXT }, /* rw */ - { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT | F_REG_READ }, /* ro */ + { "pmsidr_el1", CPENC (3, 0, C9, C9, 7), F_ARCHEXT }, /* rw */ { "pmscr_el2", CPENC (3, 4, C9, C9, 0), F_ARCHEXT }, /* rw */ { "pmscr_el12", CPENC (3, 5, C9, C9, 0), F_ARCHEXT }, /* rw */ { "pmcr_el0", CPENC(3,3,C9,C12, 0), 0 }, |