riscv-gnu-toolchain/gdb.git - Unnamed repository; edit this file 'description' to name the repository.

Age	Commit message (Expand)	Author	Files	Lines
2023-11-07	RISC-V: Add support for XCValu extension in CV32E40P	Mary Bennett	1	-0/+4
2023-11-07	RISC-V: Add support for XCVmac extension in CV32E40P	Mary Bennett	1	-0/+11
2023-10-13	RISC-V: Add support for numbered ISA mapping strings	Joseph Faulls	1	-1/+15
2023-09-07	RISC-V: Clarify the naming rules of vendor operands.	Nelson Chu	1	-81/+86
2023-08-15	RISC-V: remove indirection from register tables	Jan Beulich	1	-6/+6
2023-08-02	Revert "2.41 Release sources"	Sam James	1	-1/+15
2023-08-02	2.41 Release sourcesbinutils-2_41-release	Nick Clifton	1	-15/+1
2023-07-28	Fix typo in riscv-dis.c comment	Tsukasa OI	1	-1/+1
2023-07-18	RISC-V: Supports Zcb extension.	Jiawei	1	-0/+14
2023-07-01	RISC-V: Add support for the Zvbb ISA extension	Christoph Müllner	1	-0/+4
2023-06-30	RISC-V: Add support for the Zfa extension	Christoph Müllner	1	-0/+16
2023-05-19	RISC-V: Minor improvements for dis-assembler.	Nelson Chu	1	-21/+37
2023-04-18	RISC-V: Cache the latest mapping symbol and its boundary.	Kito Cheng	1	-0/+43
2023-03-31	RISC-V: Allocate "various" operand type	Tsukasa OI	1	-5/+21
2023-03-21	RISC-V: Fix disassemble fetch fail return value.	Jiawei	1	-2/+2
2023-02-03	RISC-V: don't disassemble unrecognized insns as .byte	Jan Beulich	1	-30/+20
2023-01-01	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2022-11-28	RISC-V: Better support for long instructions (disassembler)	Tsukasa OI	1	-5/+9
2022-10-28	RISC-V: Output mapping symbols with ISA string.	Nelson Chu	1	-0/+9
2022-10-14	opcodes/riscv-dis.c: Remove last_map_state	Tsukasa OI	1	-3/+0
2022-10-14	opcodes/riscv-dis.c: Make XLEN variable static	Tsukasa OI	1	-1/+1
2022-10-14	opcodes/riscv-dis.c: Use bool type whenever possible	Tsukasa OI	1	-5/+5
2022-10-14	opcodes/riscv-dis.c: Tidying with spacing	Tsukasa OI	1	-1/+1
2022-10-14	opcodes/riscv-dis.c: Tidying with comments/clarity	Tsukasa OI	1	-4/+21
2022-10-06	RISC-V: Print XTheadMemPair literal as "immediate"	Tsukasa OI	1	-1/+1
2022-10-06	RISC-V: Fix T-Head immediate types on printing	Tsukasa OI	1	-4/+4
2022-10-06	RISC-V: Print comma and tabs as the "text" style	Tsukasa OI	1	-11/+20
2022-10-06	RISC-V: Optimize riscv_disassemble_data printf	Tsukasa OI	1	-6/+4
2022-10-06	RISC-V: Fix printf argument types corresponding %x	Tsukasa OI	1	-7/+7
2022-10-06	RISC-V: Fix immediates to have "immediate" style	Tsukasa OI	1	-5/+5
2022-10-04	RISC-V: Fix buffer overflow on print_insn_riscv	Tsukasa OI	1	-1/+1
2022-10-04	opcodes/riscv: style csr names as registers	Andrew Burgess	1	-1/+2
2022-09-30	RISC-V: fix build after "Add support for arbitrary immediate encoding formats"	Jan Beulich	1	-2/+2
2022-09-22	RISC-V: Add support for literal instruction arguments	Christoph Müllner	1	-0/+9
2022-09-22	RISC-V: Add support for arbitrary immediate encoding formats	Christoph Müllner	1	-0/+34
2022-09-22	RISC-V: Remove "b" operand type from disassembler	Tsukasa OI	1	-1/+0
2022-09-06	opcodes: Add non-enum disassembler options	Tsukasa OI	1	-0/+2
2022-09-02	RISC-V: Print highest address (-1) on the disassembler	Tsukasa OI	1	-6/+14
2022-09-02	RISC-V: PR29342, Fix RV32 disassembler address computation	Tsukasa OI	1	-1/+7
2022-07-07	RISC-V: Fix disassembling Zfinx with -M numeric	Tsukasa OI	1	-1/+1
2022-04-30	opcodes: don't assume ELF in riscv, csky, rl78, mep disassemblers	Thomas Hebb	1	-16/+12
2022-04-04	opcodes/riscv: implement style support in the disassembler	Andrew Burgess	1	-72/+121
2022-03-18	RISC-V: Prefetch hint instructions and operand set	Tsukasa OI	1	-0/+4
2022-01-02	Update year range in copyright notice of binutils files	Alan Modra	1	-1/+1
2021-11-30	RISC-V: The vtype immediate with more than the defined 8 bits are preserved.	Nelson Chu	1	-1/+1
2021-11-30	RISC-V: Dump vset[i]vli immediate as numbers once vsew or vlmul is reserved.	Nelson Chu	1	-1/+3
2021-11-26	opcodes/riscv: add disassembler options support to libopcodes	Andrew Burgess	1	-9/+138
2021-11-18	RISC-V: Add instructions and operand set for z[fdq]inx	jiawei	1	-0/+4
2021-11-17	RISC-V: Support rvv extension with released version 1.0.	Nelson Chu	1	-0/+67
2021-11-16	RISC-V: Scalar crypto instructions and operand set.	jiawei	1	-0/+8