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path: root/opcodes/riscv-dis.c
AgeCommit message (Expand)AuthorFilesLines
2021-10-27RISC-V: Tidy riscv assembler and disassembler.Nelson Chu1-8/+10
2021-09-20riscv: print .2byte or .4byte before an unknown instruction encodingAndrew Burgess1-1/+23
2021-09-08RISC-V: Pretty print values formed with lui and addiw.Jim Wilson1-5/+18
2021-08-30RISC-V: PR28291, Fix the gdb fails that PR27916 caused.Nelson Chu1-2/+2
2021-08-30RISC-V: PR27916, Support mapping symbols.Nelson Chu1-12/+233
2021-05-18RISC-V: PR27814, Objdump crashes when disassembling a non-ELF RISC-V binary.Job Noorman1-10/+14
2021-03-31Use bool in opcodesAlan Modra1-7/+7
2021-03-31Remove bfd_stdint.hAlan Modra1-1/+1
2021-02-19RISC-V: PR27158, fixed UJ/SB types and added CSS/CL/CS types for .insn.Nelson Chu1-20/+17
2021-02-18RISC-V: Add bfd/cpu-riscv.h to support all spec versions controlling.Nelson Chu1-8/+13
2021-01-15RISC-V: Error and warning messages tidy.Nelson Chu1-1/+1
2021-01-15RISC-V: Comments tidy and improvement.Nelson Chu1-15/+13
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-12-10RISC-V: Dump CSR according to the elf privileged spec attributes.Nelson Chu1-3/+34
2020-06-30RISC-V: Support debug and float CSR as the unprivileged ones.Nelson Chu1-3/+6
2020-06-22RISC-V: Report warning when linking the objects with different priv specs.Nelson Chu1-0/+1
2020-05-20[PATCH v2 0/9] RISC-V: Support version controling for ISA standard extensions...Nelson Chu1-10/+70
2020-02-20RISC-V: Support the ISA-dependent CSR checking.Nelson Chu1-1/+1
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-06-26RISC-V: Make objdump disassembly work right for binary files.Jim Wilson1-1/+5
2019-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2018-12-18Include bfd_stdint.h in bfd.hAlan Modra1-1/+1
2018-12-06opcodes/riscv: Hide '.L0 ' fake symbolsAndrew Burgess1-0/+17
2018-12-03RISC-V: Accept version, supervisor ext and more than one NSE for -march.Jim Wilson1-1/+1
2018-08-30RISC-V: Allow instruction require more than one extensionJim Wilson1-1/+1
2018-07-30RISC-V: Set insn info fields correctly when disassembling.Jim Wilson1-0/+26
2018-03-03opcodes error messagesAlan Modra1-2/+2
2018-01-09RISC-V: Disassemble x0 based addresses as 0.Jim Wilson1-1/+1
2018-01-05RISC-V: Print symbol address for jalr w/ zero offset.Jim Wilson1-0/+2
2018-01-03Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2017-07-25Fix typos in error and option messages in OPCODES library.Nick Clifton1-1/+1
2017-05-24Move print_insn_XXX to an opcodes internal headerYao Qi1-1/+1
2017-05-04RISC-V: Fix disassemble for c.li, c.andi and c.addiwKito Cheng1-0/+1
2017-04-04RISC-V: Resurrect GP-relative disassembly hintsPalmer Dabbelt1-1/+1
2017-01-03Add fall through comment.Dilyan Palauzov1-0/+1
2017-01-02Update year range in copyright notice of all files.Alan Modra1-1/+1
2016-12-20Re-work RISC-V gas flags: now we just support -mabi and -marchAndrew Waterman1-2/+6
2016-11-01Add support for RISC-V architecture.Nick Clifton1-0/+502