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path: root/opcodes/i386-opc.tbl
AgeCommit message (Expand)AuthorFilesLines
2018-08-11x86: Add CpuCMOV and CpuFXSRH.J. Lu1-34/+34
2018-08-03x86: drop NoRex64 from {,v}pmov{s,z}x*Jan Beulich1-24/+24
2018-07-31x86: also optimize KXOR{D,Q} and KANDN{D,Q}Jan Beulich1-4/+4
2018-07-31x86: fold various AVX512 templates with so far differing Masking attributesJan Beulich1-155/+91
2018-07-31x86/Intel: correct permitted operand sizes for AVX512 scatter/gatherJan Beulich1-62/+62
2018-07-24x86-64: correct AVX512F vcvtsi2s{d,s} handlingJan Beulich1-8/+8
2018-07-19x86: fold narrowing VCVT* templatesJan Beulich1-39/+30
2018-07-19x86: fold VFPCLASSP{D,S} templatesJan Beulich1-13/+9
2018-07-19x86: fold various AVX512* templatesJan Beulich1-117/+35
2018-07-19x86: fold various AVX512DQ templatesJan Beulich1-58/+20
2018-07-19x86: fold various AVX512BW templatesJan Beulich1-309/+106
2018-07-19x86: fold various AVX512CD templatesJan Beulich1-20/+4
2018-07-19x86: fold various AVX512VL templates into their AVX512F counterpartsJan Beulich1-978/+326
2018-07-19x86: pre-process opcodes table before parsingJan Beulich1-0/+6
2018-07-18x86: Split vcvtps2{,u}qq and vcvttps2{,u}qqH.J. Lu1-4/+8
2018-07-11x86: adjust monitor/mwait templatesJan Beulich1-14/+12
2018-07-11x86/Intel: accept memory operand size specifiers for CET insnsJan Beulich1-4/+4
2018-06-01x86: fold MOV to/from segment register templatesJan Beulich1-10/+4
2018-06-01x86: don't emit REX.W for SLDT and STRJan Beulich1-2/+2
2018-06-01x86/Intel: accept "oword ptr" for INVPCIDJan Beulich1-2/+2
2018-05-09x86: Remove Disp<N> from movidir{i,64b}H.J. Lu1-3/+3
2018-05-07Enable Intel MOVDIRI, MOVDIR64B instructionsH.J. Lu1-0/+9
2018-05-07x86: Replace AddrPrefixOp0 with AddrPrefixOpRegH.J. Lu1-10/+10
2018-04-27Revert "Enable Intel MOVDIRI, MOVDIR64B instructions."Igor Tsimbalist1-10/+0
2018-04-26Enable Intel MOVDIRI, MOVDIR64B instructions.Igor Tsimbalist1-0/+10
2018-04-26x86: fold various non-memory operand AVX512VL templatesJan Beulich1-228/+148
2018-04-26x86: drop VexImmExtJan Beulich1-70/+70
2018-04-25x86: drop redundant AVX512VL shift templatesJan Beulich1-6/+0
2018-04-17Enable Intel CLDEMOTE instruction.Igor Tsimbalist1-0/+6
2018-04-15x86: Allow 32-bit registers for tpause and umwaitH.J. Lu1-4/+2
2018-04-11Enable Intel WAITPKG instructions.Igor Tsimbalist1-0/+13
2018-03-28x86: drop VecESizeJan Beulich1-543/+543
2018-03-28x86: convert broadcast insn attribute to booleanJan Beulich1-1085/+1085
2018-03-28x86: fold to-scalar-int conversion insnsJan Beulich1-43/+21
2018-03-22x86: drop pointless VecESizeJan Beulich1-477/+477
2018-03-22x86: drop remaining redundant DispNJan Beulich1-75/+75
2018-03-22x86: fix swapped operand handling for BNDMOVJan Beulich1-2/+2
2018-03-22x86/Intel: fix fallout from earlier template foldingJan Beulich1-10/+15
2018-03-22x86: fold a few XOP templatesJan Beulich1-16/+8
2018-03-08x86-64: Also optimize "clr reg64"H.J. Lu1-1/+1
2018-03-08x86: Remove support for old (<= 2.8.1) versions of gccH.J. Lu1-8/+0
2018-03-08x86: fold several AVX512VL templatesJan Beulich1-185/+90
2018-03-08x86: fold certain AVX512 rotate and shift templatesJan Beulich1-84/+45
2018-03-08x86: fold VEX-encoded GFNI templatesJan Beulich1-8/+3
2018-03-08x86: fold a few AVX512F templatesJan Beulich1-24/+12
2018-03-08x86: fold LWP templatesJan Beulich1-8/+4
2018-03-08x86: fold FMA and FMA4 templatesJan Beulich1-120/+60
2018-03-08x86: drop {X,Y,Z}MMWORD_MNEM_SUFFIXJan Beulich1-1/+1
2018-03-08x86: drop bogus NoAVXJan Beulich1-7/+7
2018-03-08x86: avoid SSE check for LDMXCSR/STMXCSRJan Beulich1-2/+2
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