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AgeCommit message (Expand)AuthorFilesLines
2024-10-30x86/APX: support JMPABS also in assemblerJan Beulich1-0/+3
2024-10-29x86: use <xyz> for VFPCLASSP{S,D}Jan Beulich1-5/+1
2024-10-18x86: Support x86 ZHAOXIN GMI instructionsMayShao-oc1-0/+5
2024-10-16Support Intel AVX10.2 convert instructionsLiwei Xu1-0/+19
2024-10-11Support Intel AVX10.2 media instructionsHaochen Jiang1-2/+14
2024-09-27x86: optimize {,V}INSERTPS with certain immediatesJan Beulich1-3/+3
2024-09-27x86: optimize {,V}EXTRACT{F,I}{128,32x{4,8},64x{2,4}} with immediate 0Jan Beulich1-10/+10
2024-09-27x86: optimize {,V}EXTRACTPS with immediate 0Jan Beulich1-6/+6
2024-09-26x86: templatize SIMD narrowing-move templatesJan Beulich1-63/+23
2024-09-26x86: templatize SIMD sign-/zero-extension templatesJan Beulich1-60/+29
2024-09-26x86: templatize SIMD FP binary-logic templatesJan Beulich1-16/+5
2024-09-26x86: further templatize FMA templatesJan Beulich1-16/+6
2024-09-26x86: templatize SIMD FP arithmetic templatesJan Beulich1-51/+16
2024-09-18x86/APX: Don't promote AVX/AVX2 instructions out of APX specH.J. Lu1-16/+0
2024-09-06x86/APX: use D for 2-operand CFCMOVccJan Beulich1-2/+1
2024-09-06x86/APX: optimize certain reg-only CFCMOVcc formsJan Beulich1-1/+1
2024-09-06x86: templatize VNNI templatesJan Beulich1-26/+17
2024-09-02Support ymm rounding control for Intel AVX10.2Haochen Jiang1-20/+20
2024-07-26x86/APX: optimize certain {nf}-form insns to BMI2 onesJan Beulich1-14/+14
2024-07-04Support APX CFCMOVCui, Lili1-0/+5
2024-06-28x86/APX: apply NDD-to-legacy transformation to further CMOVcc formsJan Beulich1-1/+4
2024-06-28x86/APX: extend TEST-by-imm7 optimization to CTESTccJan Beulich1-2/+2
2024-06-28x86/APX: optimize {nf}-form IMUL-by-power-of-2 to SHLJan Beulich1-6/+6
2024-06-28x86/APX: optimize certain {nf}-form insns to LEAJan Beulich1-3/+3
2024-06-28x86/APX: optimize {nf}-form rotate-by-width-less-1Jan Beulich1-11/+11
2024-06-28x86/APX: optimize {nf} forms of ADD/SUB with specific immediatesJan Beulich1-12/+12
2024-06-21x86: optimize {,V}PEXTR{D,Q} with immediate of 0Jan Beulich1-6/+6
2024-06-21x86: optimize left-shift-by-1Jan Beulich1-28/+28
2024-06-19x86: Remove the secondary encoding for ctest.Cui, Lili1-1/+0
2024-06-18Support APX CCMP and CTESTCui, Lili1-0/+19
2024-06-10x86/APX: convert ZU to operand constraintJan Beulich1-2/+5
2024-06-10x86/APX: support extended SETcc formJan Beulich1-1/+4
2024-06-10x86/APX: add missing CPU requirement to imm+rm forms of <alu2> insnsJan Beulich1-1/+1
2024-05-29x86/Intel: warn about undue mnemonic suffixesJan Beulich1-87/+87
2024-05-24x86: correct VCVT{,U}SI2SDJan Beulich1-8/+8
2024-05-22Support APX zero-upperCui, Lili1-0/+6
2024-05-06x86: Drop using extension_opcode to encode vvvv registerCui, Lili1-59/+61
2024-05-06x86: Drop SwapSourcesCui, Lili1-30/+30
2024-05-06x86: Use vexvvvv as the switch state to encode the vvvv registerCui, Lili1-565/+566
2024-05-03x86: tidy <sse*> templatesJan Beulich1-20/+20
2024-05-03x86/APX: further extend SSE2AVX coverageJan Beulich1-5/+6
2024-05-03x86/APX: extend SSE2AVX coverageJan Beulich1-201/+303
2024-04-17Add W table for USER_MSR under MAP4.Hu, Lin11-1/+1
2024-04-07Support APX NFCui, Lili1-2/+21
2024-04-06Revert "x86: Restore APX shift-double instructions with omitted shift count"H.J. Lu1-1/+0
2024-04-04x86: Restore APX shift-double instructions with omitted shift countH.J. Lu1-0/+1
2024-04-03x86: add missing No_qSuf to non-64-bit PTWRITEJan Beulich1-1/+1
2024-04-03x86: drop stray Size64 from WRSSQJan Beulich1-2/+2
2024-04-03x86/APX: Remove KEYLOCKER and SHA promotions from EVEX MAP4Cui, Lili1-18/+0
2024-03-28x86: templatize RAO-INT insnsJan Beulich1-8/+4