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path: root/opcodes/aarch64-opc-2.c
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2023-11-07aarch64: Add LSE128 instructionsVictor Do Nascimento1-15/+17
2023-11-02aarch64: Add support for GCSB DSYNC instruction.Srinath Parvathaneni1-9/+10
2023-11-02aarch64: Add support for GCS extension.srinath1-8/+9
2023-03-30aarch64: Add the RPRFM instructionRichard Sandiford1-0/+1
2023-03-30aarch64: Add new SVE dot-product instructionsRichard Sandiford1-1/+2
2023-03-30aarch64: Add the SME2 shift instructionsRichard Sandiford1-0/+2
2023-03-30aarch64: Add the SME2 MLALL and MLSLL instructionsRichard Sandiford1-0/+5
2023-03-30aarch64: Add the SME2 MLAL and MLSL instructionsRichard Sandiford1-0/+4
2023-03-30aarch64: Add the SME2 FMLA and FMLS instructionsRichard Sandiford1-0/+2
2023-03-30aarch64: Add the SME2 ADD and SUB instructionsRichard Sandiford1-0/+1
2023-03-30aarch64: Add the SME2 ZT0 instructionsRichard Sandiford1-0/+9
2023-03-30aarch64: Add the SME2 predicate-related instructionsRichard Sandiford1-0/+10
2023-03-30aarch64: Add the SME2 multivector LD1 and ST1 instructionsRichard Sandiford1-0/+3
2023-03-30aarch64: Add the SME2 MOVA instructionsRichard Sandiford1-0/+8
2023-03-30aarch64: Add support for predicate-as-counter registersRichard Sandiford1-6/+11
2023-03-30aarch64: Add _off4 suffix to AARCH64_OPND_SME_ZA_arrayRichard Sandiford1-1/+1
2023-03-30aarch64: Add a _10 suffix to FLD_imm3Richard Sandiford1-1/+1
2023-03-30aarch64: Regularise FLD_* suffixesRichard Sandiford1-16/+16
2023-03-30aarch64: Add an operand class for SVE register listsRichard Sandiford1-2/+2
2023-03-30aarch64: Move ZA range checks to aarch64-opc.cRichard Sandiford1-4/+4
2023-03-30aarch64: Treat ZA as a registerRichard Sandiford1-1/+1
2023-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2022-11-14aarch64: Add support for Common Short Sequence Compression extensionAndre Vieira1-0/+2
2022-10-05Arm64: support CLEARBHB aliasJan Beulich1-8/+8
2022-01-02Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2021-12-02aarch64: Add support for +mopsRichard Sandiford1-0/+3
2021-11-17aarch64: [SME] SVE2 instructions added to support SMEPrzemyslaw Wirkus1-0/+1
2021-11-17aarch64: [SME] Add SME mode selection and state access instructionsPrzemyslaw Wirkus1-9/+10
2021-11-17aarch64: [SME] Add LD1x, ST1x, LDR and STR instructionsPrzemyslaw Wirkus1-0/+4
2021-11-17aarch64: [SME] Add ZERO instructionPrzemyslaw Wirkus1-0/+1
2021-11-17aarch64: [SME] Add MOV and MOVA instructionsPrzemyslaw Wirkus1-0/+2
2021-11-17aarch64: [SME] Add SME instructionsPrzemyslaw Wirkus1-0/+3
2021-01-11aarch64: Remove support for CSREKyrylo Tkachov1-8/+8
2021-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2020-11-09aarch64: Limit Rt register number for LS64 load/store instructionsPrzemyslaw Wirkus1-0/+1
2020-11-03[PATCH][GAS] aarch64: Add atomic 64-byte load/store instructions for Armv8.7Przemyslaw Wirkus1-16/+16
2020-10-30[PATCH][GAS] aarch64: Add WFIT instruction for Armv8.7-aPrzemyslaw Wirkus1-8/+8
2020-10-28aarch64: Add CSR PDEC instructionPrzemyslaw Wirkus1-8/+8
2020-10-28aarch64: Add WFET instruction for Armv8.7-aPrzemyslaw Wirkus1-8/+8
2020-10-28aarch64: Add DSB instruction Armv8.7-a variantPrzemyslaw Wirkus1-8/+9
2020-09-08aarch64: Add support for Armv8-R DFB aliasAlex Coplan1-8/+8
2020-04-30AArch64: add GAS support for UDF instructionAlex Coplan1-26/+27
2020-04-20[AArch64, Binutils] Add missing TSB instructionSudakshina Das1-9/+9
2020-04-20[AArch64, Binutils] Make hint space instructions valid for Armv8-aSudakshina Das1-8/+8
2020-01-27AArch64: Fix cfinv disassembly issuesTamar Christina1-8/+8
2020-01-01Update year range in copyright notice of binutils filesAlan Modra1-1/+1
2019-11-07[binutils][aarch64] Matrix Multiply extension enablement [8/X]Matthew Malcomson1-0/+1
2019-10-30Modify the ARNM assembler to accept the omission of the immediate argument fo...Delia Burduv1-1/+1
2019-05-09[binutils][aarch64] New SVE_SHLIMM_UNPRED_22 operand.Matthew Malcomson1-0/+1
2019-05-09[binutils][aarch64] New SVE_Zm4_11_INDEX operand.Matthew Malcomson1-0/+1
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