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| author | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2022-11-14 16:47:22 +0000 |
|---|---|---|
| committer | Andre Vieira <andre.simoesdiasvieira@arm.com> | 2022-11-14 16:47:22 +0000 |
| commit | 1f7b42d52a8cb690c259eaa4975a608e82d7267a (patch) | |
| tree | 8e0d1faeeb5f8cfb1cf2caf218936c625ac46e98 /opcodes/aarch64-opc-2.c | |
| parent | 255571cdbf05213cc96feefb779c4158df453398 (diff) | |
| download | gdb-1f7b42d52a8cb690c259eaa4975a608e82d7267a.zip gdb-1f7b42d52a8cb690c259eaa4975a608e82d7267a.tar.gz gdb-1f7b42d52a8cb690c259eaa4975a608e82d7267a.tar.bz2 | |
aarch64: Add support for Common Short Sequence Compression extension
This patch adds support for the CSSC extension and its corresponding
instructions: ABS, CNT, CTZ, SMAX, UMAX, SMIN, UMIN.
gas/ChangeLog:
* config/tc-aarch64.c (parse_operands): Handle new operand types.
* doc/c-aarch64.texi: Document new extension.
* testsuite/gas/aarch64/cssc.d: New test.
* testsuite/gas/aarch64/cssc.s: New test.
include/ChangeLog:
* opcode/aarch64.h (AARCH64_FEATURE_CSSC): New feature Macro.
(enum aarch64_opnd): New operand types.
(enum aarch64_insn_class): New instruction class.
opcodes/ChangeLog:
* aarch64-asm-2.c: Regenerate.
* aarch64-dis-2.c: Regenerate.
* aarch64-opc-2.c: Regenerate.
* aarch64-opc.c (operand_general_constraint_met_p): Update for new
operand types.
(aarch64_print_operand): Likewise.
* aarch64-opc.h (enum aarch64_field_kind): Declare FLD_CSSC_imm8 field.
* aarch64-tbl.h (aarch64_feature_cssc): Define new feature set.
(CSSC): Define new feature set Macro.
(CSSC_INSN): Define new instruction type.
(aarch64_opcode_table): Add new instructions.
Diffstat (limited to 'opcodes/aarch64-opc-2.c')
| -rw-r--r-- | opcodes/aarch64-opc-2.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/opcodes/aarch64-opc-2.c b/opcodes/aarch64-opc-2.c index a6ef709..b680225 100644 --- a/opcodes/aarch64-opc-2.c +++ b/opcodes/aarch64-opc-2.c @@ -250,6 +250,8 @@ const struct aarch64_operand aarch64_operands[] = {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rd}, "a register destination address with writeback"}, {AARCH64_OPND_CLASS_INT_REG, "MOPS_ADDR_Rs", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rs}, "a register source address with writeback"}, {AARCH64_OPND_CLASS_INT_REG, "MOPS_WB_Rd", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_Rn}, "an integer register with writeback"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_SIMM8", OPD_F_SEXT | OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit signed immediate"}, + {AARCH64_OPND_CLASS_IMMEDIATE, "CSSC_UIMM8", OPD_F_HAS_INSERTER | OPD_F_HAS_EXTRACTOR, {FLD_CSSC_imm8}, "an 8-bit unsigned immediate"}, {AARCH64_OPND_CLASS_NIL, "", 0, {0}, "DUMMY"}, }; |