aboutsummaryrefslogtreecommitdiff
path: root/opcodes/ChangeLog
AgeCommit message (Expand)AuthorFilesLines
2017-10-18[Visium] Disassemble the operands of the stop instruction.Eric Botcazou1-0/+4
2017-10-12FT32: support for FT32B processor - part 1James Bowman1-0/+6
2017-10-09S/390: Sync with latest POP - 3 new instructionsAndreas Krebbel1-0/+4
2017-10-09S/390: Sync with IBM z14 POP - SI_RD formatAndreas Krebbel1-0/+7
2017-10-01Add new mnemonics for VLE multiple load instructionsAlexander Fedotov1-0/+8
2017-09-27Add support for the new names of the RISC-V fmv.x.s and fmv.s.x instructions,...Nick Clifton1-0/+6
2017-09-26Allow the macw and macl instructions to be used on CPUs that have emacs support.Nick Clifton1-0/+6
2017-09-25Initialize 'imm' on opcodes/aarch64-opc.c:expand_fp_imm (and fix breakage on ...Sergio Durigan Junior1-0/+4
2017-09-11nds32: Rename __BIT() to N32_BIT().Kuan-Lin Chen1-0/+6
2017-09-09x86: Remove restriction on NOTRACK prefix positionH.J. Lu1-0/+6
2017-08-31Add updated French translations for opcodes and gprofNick Clifton1-0/+4
2017-08-30FT32: improve disassembly readabilityJames Bowman1-0/+5
2017-08-24[PowerPC VLE] Add SPE2 and EFS2 instructions supportAlexander Fedotov1-0/+60
2017-08-23ppc-opc.c formattingAlan Modra1-0/+7
2017-08-22RISC-V: Mark "c.nop" as an aliasPalmer Dabbelt1-0/+4
2017-08-21[PowerPC VLE] Add LSP (Lightweight Signal Processing) instruction supportAlexander Fedotov1-0/+34
2017-08-09[ARM] Don't warn on REG_SP when used in CRC32 instructionsJiong Wang1-0/+7
2017-08-07Mark big and mach with ATTRIBUTE_UNUSEDH.J. Lu1-0/+5
2017-08-07GDB/opcodes: Remove arch/mach/endian disassembler assertionsMaciej W. Rozycki1-0/+5
2017-07-25Fix typos in error and option messages in OPCODES library.Nick Clifton1-0/+39
2017-07-24[AArch64] Fix the bit pattern order in the comments in auto-generated fileJiong Wang1-0/+7
2017-07-21S/390: Support z14 as CPU name.Andreas Krebbel1-0/+5
2017-07-20Update the German translation for the opcodes library.Nick Clifton1-0/+4
2017-07-19[ARC] Add SecureShield AUX registersclaziss1-0/+12
2017-07-19[ARC] Add SJLI instruction.Claudiu Zissulescu1-0/+7
2017-07-19[ARC] Add JLI support.John Eric Martin1-0/+8
2017-07-18Fix spelling typos.Yuri Chornovian1-0/+6
2017-07-14binutils/objdump: Fix disassemble for huge elf sectionsRavi Bangoria1-0/+5
2017-07-12Update PO filesAlan Modra1-0/+18
2017-07-11Mark generated cgen files read-onlyAlan Modra1-0/+99
2017-07-07Move print_insn_XXX to an opcodes internal header, againAlan Modra1-0/+6
2017-07-05X86: Disassemble primary opcode map's group 2 ModRM.reg == 6 aliases correctlyBorislav Petkov1-0/+4
2017-07-05Fixup changelog entries for previous commitRamana Radhakrishnan1-0/+5
2017-07-04Regenerate configure.Tristan Gingold1-0/+4
2017-07-03Regenerate pot files.Tristan Gingold1-0/+4
2017-06-30MIPS/opcodes: Reorder LSA and DLSA instructionsMaciej W. Rozycki1-0/+5
2017-06-30MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor support (ChangeLog)Maciej W. Rozycki1-1/+1
2017-06-30MIPS: Add microMIPS XPA supportMaciej W. Rozycki1-0/+7
2017-06-30MIPS: Add microMIPS R5 supportMaciej W. Rozycki1-0/+6
2017-06-30MIPS: Fix XPA base and Virtualization ASE instruction handlingMaciej W. Rozycki1-0/+12
2017-06-30MIPS/opcodes: Correctly combine ASE flags for ASE_MIPS16E2_MT calculationMaciej W. Rozycki1-0/+7
2017-06-29[ARC] Use FOR_EACH_DISASSEMBLER_OPTION to iterate over optionsAnton Kolesov1-0/+5
2017-06-29[ARC] Fix handling of cpu=... disassembler option valueAnton Kolesov1-0/+6
2017-06-28[AArch64] Add dot product support for AArch64 to binutilsTamar Christina1-0/+9
2017-06-28[ARM] Assembler and disassembler support Dot Product ExtensionJiong Wang1-0/+4
2017-06-28MIPS: Add Imagination interAptiv MR2 MIPS32r3 processor supportMaciej W. Rozycki1-0/+21
2017-06-23RISC-V: Fix SLTI disassemblyAndrew Waterman1-0/+5
2017-06-21x86: CET v2.0: Update incssp and setssbsyH.J. Lu1-0/+15
2017-06-21x86: CET v2.0: Rename savessp to saveprevsspH.J. Lu1-0/+6
2017-06-21x86: CET v2.0: Update NOTRACK prefixH.J. Lu1-0/+7
generated by cgit v1.1 at 2024-07-13 14:13:20 +0000